THS8083A Datasheet, PDF (14/64 Pages) Texas Instruments – TRIPLE 8 BIT 80 MSPS 3.3V VIDEO AND GRAPHICS

1.7 THS8083A Terminal Functions Order (Continued)
TERMINAL
NAME
NO.
I/O/B^† TYPE^‡
DESCRIPTION
SCL
SDA
I2CA
DIGITAL CONTROL I/O
3
B
D Clock for I2C. Although the device is an I2C slave, this signal can be held low by the device
to signal contention, therefore it is flagged bidirectional.
4
B
D Serial data for I2C
5
I
D Address select for I2C
0 = LSB of device address 0
1 = LSB of device address 1
EXT_CLP
HS
VS
99
I
D External clamp timing pulse. Positive polarity required.
1
I
D Reference clock input for PLL (horizontal sync input). Polarity selectable via I2C register
<HS_POL>. 5-V tolerant input
2
I
D Vertical sync input. Polarity selectable via I2C register <VS_POL>. 5 V tolerant input
DHS
55
O
D Display horizontal sync. This output can be generated as either a delayed version of
input HS or as output pulse from the PLL feedback divider. See Display Horizontal
Sync section in Functional Description.
CS/TEST1
78
O
A/D Composite sync output. This output produces a 3-V logic-compatible sliced output of
CH1 or CS_IN, depending on CS_SEL (see CS_IN/TEST2 terminal). When present
and enabled, CS carries the embedded composite sync. See Composite Sync Slicer
section in Functional Description. For TI internal testing, this pin can also be configured
as a test pin. Leave unconnected when CS output signal is not used.
CS_IN/TEST2
79
I
A Composite sync slicing input. When selected by CS_SEL register, the signal on this pin
is clamped to blanking level according to the clamp timing pulse and sliced approxi-
mately 150 mV below this clamped level to produce a composite sync output available
on CS/TEST1. This pin can also be configured as a test pin for TI internal testing.
Leave unconnected when CS input signal is not used.
LOCK
100
O
D Lock detect output
0 = unlocked
1 = locked
PFD_FREEZE
98
I
D Freezes the PLL output frequency by stopping the PFD output (i.e., keeping last
increment to DTO). See section 2.3 Composite Sync Slicer.
0 = updating
1 = frozen
OE
71
I
D Output enable for data output busses A and B. Data outputs are active only when
OE = L and the corresponding bus is active for the current output formatter mode
(register OFM_CTRL). When data outputs are not active or when DVDD = 0 V, data
output is Hi-Z. The clock outputs are not affected by OE.
0 = enabled
1 = disabled
RESET
76
I
D General chip reset (active low). The reset is a synchronous reset. Therefore, a master
clock on XTL1–MCLK needs to be present for proper reset.
TEST I/O
CS/TEST1
78
O
A/D See previous description for this terminal under DIGITAL CONTROL I/O.
TEST2
79
O
A/D See previous description for this terminal under DIGITAL CONTROL I/O.
SCAN_TEST
77
I
D Input for scan-path activation:
0 = disabled
1 = enabled.
This pin MUST be tied low for normal operation and is of use for TI internal testing only.
UNUSED PINS
NC
80, 86, 87,
I
93, 94
† _{I = input to device: O = output from device}
‡ _{A = analog pin: D = digital pin}
A Not connected. Tie to a fixed high or low level on board.
B = bidirectional
1–8