LP38798_15 Datasheet, PDF (20/27 Pages) Texas Instruments – LP38798 High PSRR, Ultra-Low-Noise, 800-mA Linear Voltage Regulator for RF/Analog Circuits

LP38798
SNOSCT6B – MARCH 2013 – REVISED DECEMBER 2014
www.ti.com
9 Power Supply Recommendations
The LP38798 device is designed to operate from an input voltage supply range of 3 V to 20 V. The input supply
must be able to supply enough current to keep the input voltage from drooping during load transients and high
load current. If the input supply is noisy, additional input capacitors with low ESR can help improve the output
noise performance.
10 Layout
10.1 Layout Guidelines
The dynamic performance of the LP38798 is dependant on the layout of the PCB. PCB layout practices that are
adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP38798.
Best performance is achieved by placing all of the components on the same side of the PCB as the LP38798,
and as close as is practical to the LP38798 package. All component ground connections should be back to the
LP38798 analog ground connection using as wide, and as short, of a copper trace as is practical. The connection
from the FB pin to the V_SET resistors must be as short as possible as the FB pin is a high impedance input. Any
trace length on the FB pin will act as an antenna.
Connections using long trace lengths, narrow trace widths, and connections through vias should be avoided.
These will add parasitic inductances and resistance that results in inferior performance especially during transient
conditions.
A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly
recommended. This Ground Plane serves two purposes :
1. Provides a circuit reference plane to assure accuracy, and
2. Provides a thermal plane to remove heat from the LP38798 through thermal vias under the package DAP.
10.2 Layout Example
C_IN
GND
Thermal
Vias
C_OUT
GND
V_IN
C_CP
V_EN
GND
V_OUT
R1
R2
GND
10.3 Thermal Considerations
The value of R_θJA for the 12-lead WSON package is specifically dependent on PCB copper area, copper
thickness, the number of layers, and thermal vias under the exposed thermal pad (DAP). Please refer to Texas
Instruments AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages (SNVA183)
for general guidelines for mounting packages with exposed thermal pads.
Exceeding the maximum allowable power dissipation defined by the final R_θJA will cause excessive die
temperature, and the regulator may go into thermal shutdown.
10.4 Estimating the Junction Temperature
The EIA/JEDEC standard (JESD51-2) provides methodologies to estimate the junction temperature from external
measurements (Ψ_JB references the temperature at the PCB, and Ψ_JT references the temperature at the top
surface of the package) when operating under steady-state power dissipation conditions. These methodologies
have been determined to be relatively independent of the copper thermal spreading area that may be attached to
the package DAP when compared to the more typical R_θJA. Refer to Application Report: Semiconductor and IC
Package Thermal Metrics (SPRA953), for specifics.
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