LP38798_15 Datasheet, PDF (18/27 Pages) Texas Instruments – LP38798 High PSRR, Ultra-Low-Noise, 800-mA Linear Voltage Regulator for RF/Analog Circuits

LP38798
SNOSCT6B – MARCH 2013 – REVISED DECEMBER 2014
www.ti.com
The input capacitor must be located as close as physically possible to the input pin and returned to a clean
analog ground. Any good quality tantalum capacitor may be used, while a ceramic capacitor should be X5R or
X7R rated with appropriate adjustments due to the loss of capacitance value from the applied DC voltage.
Attention must be given to the input capacitance value to minimize transient input voltage droop during load
current steps at the OUT pin. Larger input capacitor values are necessary for good transient load response, and
have no detrimental influence on the stability of the device. Note, however, that using large value ceramic input
capacitances can also cause unwanted ringing at the output if the input capacitor, in combination with the trace
inductance, creates a high-Q peaking effect during transients. Short, well-designed interconnect leads to the up-
stream supply minimize this effect without adding damping. Damping of unwanted ringing can be accomplished
by using a tantalum capacitor, with a few hundred milli-ohms of ESR, in parallel with the ceramic input capacitor.
8.2.2.2 Output Capacitor Recommendations
The LP38798 requires an output capacitance of at least 1 µF, ceramic or tantalum, however a minimum output
capacitance of 10 µF is strongly recommended if fast load transient conditions are expected. While the LP38798
is designed to work with Ceramic output capacitors, the output capacitor can be Ceramic, Tantalum, or a
combination. The total output capacitance should be sized appropriately to handle any fast load current steps.
Capacitance type, tolerance, ESR, as well as temperature and voltage characteristics, must be considered when
selecting an output capacitor for the application.
Note especially that the output capacitances must be located as near as practical to the OUT pins.
Even though the LP38798 is stable with an output capacitance of 1 µF to 10 µF, a single output capacitor will
generally not be able to provide the best PSRR performance across a wide frequency range. Multiple parallel
capacitors, each with a different self-resonance frequency will provide better performance over a wider frequency
range.
The LP38798 is characterized with a ceramic capacitor of 10 µF, or greater, at the output. Noise performance is
characterized using a single output capacitor of 10 µF ±10%, 16V, X7R, 1206.
8.2.2.3 Charge Pump
The charge pump is running when both the input voltage is above the UVLO threshold (2.65 V typical) and the
EN pin voltage is above the V_EN(ON) threshold (1.24 V typical). The typical charge pump operating frequency is
3.5 MHz.
A low leakage 10 nF X7R storage capacitor is required between the CP pin and ground to store the energy
required for gate drive of the internal NMOS pass device. Larger values of capacitance may slow start-up times,
while smaller capacitance values may result in degraded dynamic performance.
Do not make any other connection to the CP pin. Loading this pin in any manner will degrade regulator
performance. No external biasing may be applied to, or derived from, this pin, as permanent damage to the
internal charge pump circuitry may occur.
8.2.2.4 Setting the Output Voltage
The output voltage is buffered from the SET pin. The output voltage is defined as:
V_OUT = V_SET = (V_FB × ( 1 + (R1 / R2))
where
• V_FB = 1.2 V (typical)
• Value for R2 = 12.9 kΩ and 100 kΩ.
(9)
Selecting a standard 1% resistor value of 13.3 kΩ, the resistor value for R1 is calculated from:
R1 = R2 × (( V_OUT / V_FB) – 1 )
(10)
R1 = 15 kΩ × ((5 V / 1.2 V) – 1)
(11)
R1 = 47.5 kΩ
(12)
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