LP38798_15 Datasheet, PDF (14/27 Pages) Texas Instruments – LP38798 High PSRR, Ultra-Low-Noise, 800-mA Linear Voltage Regulator for RF/Analog Circuits

LP38798
SNOSCT6B – MARCH 2013 – REVISED DECEMBER 2014
7 Detailed Description
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7.1 Overview
The LP38798 is a positive voltage (20 V), ultra-low-noise (5 µV_RMS), low-dropout (LDO) regulator capable of
supplying a well-regulated, low-noise voltage to an 800-mA load. The LP38798 uses an advanced design with a
CMOS process to deliver ultra low output noise and high PSRR at switching power supply (SMPS) frequencies.
7.2 Functional Block Diagram
IN
LP38798SD-ADJ
OUT
IN
IN(CP)
CP
EN
Active Ripple
Rejection
200 mV
PMOS
Current
Limit
UVLO
Thermal
Shutdown
Charge Pump
3.5 MHz
tau= 2s
I_EN
2 2A
I_SET
52 2A
5V
1.24V
V_REF
1.200V
OUT
OUT(FB)
98%
SET
99.5%
FB
GND(CP)
GND
7.3 Feature Description
7.3.1 Noise Filter
Any noise at LP38798 SET pin is reduced by an internal passive, first order low-pass RC filter before it is passed
to the output buffer stage. The low-pass filter has a –3-dB cut-off frequency of approximately 0.08 Hz.
To keep the low-pass filter from interfering with the output voltage rise time at start-up, a voltage comparator
keeps the filter in a fast-charge mode while the output voltage (V_OUT) is less than 99.5% of the SET pin voltage
(V_SET) . When the rising V_OUT is within 0.5% of V_SET the fast-charge mode ends, and V_OUT will rise the final 0.5%
based on the RC time constant (τ = 2s) of the filter.
Should V_OUT be more than 2% above the V_SET voltage, a voltage comparator will put the filter into the fast-charge
mode to allow the filter to discharge and V_OUT to fall a value closer to V_SET. When the falling V_OUT is within 2% of
V_SET the fast-charge mode ends, and V_OUT will fall the final 2% based on the RC time constant (τ = 2s) of the
filter.
If the input voltage has an extended rise time, the output voltage may exhibit a stair-case waveform as the fast-
charge mode is activated and de-activated as V_SET rises with V_IN, and V_OUT follows. Once the V_IN has risen
above the programmed V_SET voltage, and V_OUT is within 0.5% of V_SET, the stair-case behavior will end.
14
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