AMC1204-Q1_15 Datasheet, PDF (20/33 Pages) Texas Instruments – 20 MHz, Second-Order, Isolated Delta-Sigma Modulator for Current-Shunt Measurement

AMC1204-Q1
SLAS886B – JULY 2012 – REVISED JANUARY 2013
www.ti.com
An example code for an implementation of a sinc³ filter in an FPGA follows. For more information, see the
application note Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control
Applications (SBAA094), available for download at www.ti.com.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FLT is
port(RESN, MOUT, MCLK, CNR : in std_logic;
CN5 : out std_logic_vector(23 downto 0));
end FLT;
architecture RTL of FLT is
signal DN0, DN1, DN3, DN5 : std_logic_vector(23 downto 0);
signal CN1, CN2, CN3, CN4 : std_logic_vector(23 downto 0);
signal DELTA1 : std_logic_vector(23 downto 0);
begin
process(MCLK, RESn)
begin
if RESn = '0' then
DELTA1 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
if MOUT = '1' then
DELTA1 <= DELTA1 + 1;
end if;
end if;
end process;
process(RESN, MCLK)
begin
if RESN = '0' then
CN1 <= (others => '0');
CN2 <= (others => '0');
elsif MCLK'event and MCLK = '1' then
CN1 <= CN1 + DELTA1;
CN2 <= CN2 + CN1;
end if;
end process;
process(RESN, CNR)
begin
if RESN = '0' then
DN0 <= (others => '0');
DN1 <= (others => '0');
DN3 <= (others => '0');
DN5 <= (others => '0');
elsif CNR'event and CNR = '1' then
DN0 <= CN2;
DN1 <= DN0;
DN3 <= CN3;
DN5 <= CN4;
end if;
end process;
CN3 <= DN0 - DN1;
CN4 <= CN3 - DN3;
CN5 <= CN4 - DN5;
end RTL;
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