OMAP-L138_15 Datasheet, PDF (2/286 Pages) Texas Instruments – OMAP-L138 C6000™ DSP+ ARM® Processor

OMAP-L138
SPRS586I – JUNE 2009 – REVISED SEPTEMBER 2014
www.ti.com
• 16-Bit mDDR SDRAM with 256-MB Address
Space
• Three Configurable 16550-Type UART Modules:
– With Modem Control Signals
– 16-Byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO)
Interfaces
• Two Master and Slave Inter-Integrated Circuits
( I²C Bus™)
• One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address and Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Real-Time Unit
(PRU) Cores
• 32-Bit Load-Store RISC Architecture
• 4KB of Instruction RAM Per Core
• 512 Bytes of Data RAM Per Core
• PRUSS can be Disabled via Software to
Save Power
• Register 30 of Each PRU is Exported From
the Subsystem in Addition to the Normal R31
Output of the PRU Cores.
– Standard Power-Management Mechanism
• Clock Gating
• Entire Subsystem Under a Single PSC Clock
Gating Domain
– Dedicated Interrupt Controller
– Dedicated Switched Central Resource
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
• USB 2.0 OTG Port with Integrated PHY (USB0)
– USB 2.0 High- and Full-Speed Client
– USB 2.0 High-, Full-, and Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt, or
ISOC) RX and TX
• One Multichannel Audio Serial Port (McASP):
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
– FIFO Buffers for Transmit and Receive
• Two Multichannel Buffered Serial Ports (McBSPs):
– Supports TDM, I2S, and Similar Formats
– AC97 Audio Codec Interface
– Telecom Interfaces (ST-Bus, H100)
– 128-Channel TDM
– FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC):
– IEEE 802.3 Compliant
– MII Media-Independent Interface
– RMII Reduced Media-Independent Interface
– Management Data I/O (MDIO) Module
• Video Port Interface (VPIF):
– Two 8-Bit SD (BT.656), Single 16-Bit or Single
Raw (8-, 10-, and 12-Bit) Video Capture
Channels
– Two 8-Bit SD (BT.656), Single 16-Bit Video
Display Channels
• Universal Parallel Port (uPP):
– High-Speed Parallel Interface to FPGAs and
Data Converters
– Data Width on Both Channels is 8- to 16-Bit
Inclusive
– Single-Data Rate or Dual-Data Rate Transfers
– Supports Multiple Interfaces with START,
ENABLE, and WAIT Controls
• Serial ATA (SATA) Controller:
– Supports SATA I (1.5 Gbps) and SATA II
(3.0 Gbps)
– Supports All SATA Power-Management
Features
– Hardware-Assisted Native Command Queueing
(NCQ) for up to 32 Entries
– Supports Port Multiplier and Command-Based
Switching
• Real-Time Clock (RTC) with 32-kHz Oscillator and
Separate Power Rail
• Three 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose or Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
Timers)
• Two Enhanced High-Resolution Pulse Width
Modulators (eHRPWMs):
– Dedicated 16-Bit Time-Base Counter with
Period and Frequency Control
– 6 Single-Edge Outputs, 6 Dual-Edge Symmetric
Outputs, or 3 Dual-Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– Configurable as 3 Capture Inputs or 3 Auxiliary
Pulse Width Modulator (APWM) Outputs
– Single-Shot Capture of up to Four Event Time-
Stamps
• Packages:
– 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZCE Suffix], 0.65-mm Ball Pitch
– 361-Ball Pb-Free PBGA [ZWT Suffix],
0.80-mm Ball Pitch
• Commercial, Extended, or Industrial Temperature
2
OMAP-L138 C6000 DSP+ARM Processor
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