OMAP-L138_15 Datasheet, PDF (184/286 Pages) Texas Instruments – OMAP-L138 C6000™ DSP+ ARM® Processor

OMAP-L138
SPRS586I – JUNE 2009 – REVISED SEPTEMBER 2014
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Table 6-84. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option⁽²⁾⁽³⁾
NO.
PARAMETER
1.3V, 1.2V
MIN
MAX
25
t_{d(SCSL_SPC)S}
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at
slave.
P+1.5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5M+P+4
26
t_{d(SPC_SCSH)S}
Polarity = 0, Phase = 1,
Required delay from final SPI1_CLK edge ^{from SPI1_CLK falling}
before SPI1_SCS is deasserted.
Polarity = 1, Phase = 0,
from SPI1_CLK rising
P+4
0.5M+P+4
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+4
27
t_{ena(SCSL_SOMI)S}
28
t_{dis(SCSH_SOMI)S}
Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI
P+15
P+15
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-79).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
1.1V
MIN
P+1.5
MAX
0.5M+P+5
P+5
0.5M+P+5
P+5
P+17
P+17
1.0V
MIN
MAX
P+1.5
0.5M+P+6
P+6
0.5M+P+6
P+6
P+19
P+19
Table 6-85. Additional⁽¹⁾ SPI1 Slave Timings, 5-Pin Option⁽²⁾⁽³⁾
NO.
PARAMETER
25 t_{d(SCSL_SPC)S}
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
26 t_{d(SPC_SCSH)S}
Required delay from final
SPI1_CLK edge before SPI1_SCS
is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
27
t_{ena(SCSL_SOMI)S}
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
28 t_{dis(SCSH_SOMI)S}
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
29 t_{ena(SCSL_ENA)S}
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
1.3V, 1.2V
MIN
MAX
P+1.5
0.5M+P+4
P+4
0.5M+P+4
P+4
P+15
P+15
15
1.1V
MIN
MAX
P+1.5
0.5M+P+5
P+5
0.5M+P+5
P+5
P+17
P+17
17
1.0V
MIN
MAX
P+1.5
0.5M+P+6
P+6
0.5M+P+6
P+6
P+19
P+19
19
UNIT
ns
ns
ns
ns
UNIT
ns
ns
ns
ns
ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-79).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
184 Peripheral Information and Electrical Specifications
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