TMS320DM6443 Datasheet, PDF (181/202 Pages) Texas Instruments – Digital Media System on-Chip

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TMS320DM6443
Digital Media System on-Chip
SPRS282 – DECEMBER 2005
5.19 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between DM6443 and the
network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and
100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)
support.
The EMAC controls the flow of packet data from the DM6443 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
For the DM6443 Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide which describes the DM6443 EMAC peripheral in detail, see the Documentation
Support section . For a list of supported registers and register fields, see Table 5-73 [Ethernet MAC
(EMAC) Control Registers] and Table 5-74 [EMAC Statistics Registers] in this data manual.
5.19.1 EMAC Peripheral Register Description(s)
HEX ADDRESS RANGE
01C8 0000
01C8 0004
01C8 0008
01C8 0010
01C8 0014
01C8 0018
01C8 001C - 01C8 007C
01C8 0180
01C8 0184
01C8 0188
01C8 018C
01C8 0190
01C8 0194 - 01C8 019C
01C8 01A0
01C8 01A4
01C8 01A8
01C8 01AC
01C8 01B0
01C8 01B4
01C8 01B8
01C8 01BC
01C8 00C0 - 01C8 00FC
01C8 0100
01C8 0104
01C8 0108
01C8 010C
01C8 0110
01C8 0114
Table 5-73. Ethernet MAC (EMAC) Control Registers
ACRONYM
TXIDVER
TXCONTROL
TXTEARDOWN
–
RXCONTROL
RXTEARDOWN
–
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
–
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
–
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
RXBUFFEROFFSET
RXFILTERLOWTHRESH
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
Transmit Teardown Register
Reserved
Receive Control Register
Receive Teardown Register
Reserved
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
Reserved
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Reserved
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
Peripheral and Electrical Specifications 181