TMS320DM6443 Datasheet, PDF (122/202 Pages) Texas Instruments – Digital Media System on-Chip

TMS320DM6443
Digital Media System on-Chip
SPRS282 – DECEMBER 2005
HEX ADDRESS RANGE
0x01E0 0078
0x01E0 007C
0x01E0 0080 - 0x01E0 0FFF
Table 5-29. EMIFA/NAND Registers (continued)
ACRONYM
NANDF3ECC
NANDF4ECC
-
REGISTER NAME
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
Reserved
5.10.1.2 EMIFA Electrical Data/Timing
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Table 5-30. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module⁽¹⁾⁽²⁾
(see Figure 5-17 and Figure 5-18)
-594
NO.
UNIT
MIN
MAX
READS and WRITES
2 t_{w(EM_WAIT)}
Pulse duration, EM_WAIT assertion and deassertion
2E ± TBD
ns
READS
12 t_{su(EMDV-EMOEH)}
Setup time, EM_D[15:0] valid before EM_OE high
E
ns
13 t_{h(EMOEH-EMDIV)}
Hold time, EM_D[15:0] valid after EM_OE high
0
ns
14 t_{d(EMOEL-EMWAIT)}
Delay time from EM_OE low to EM_WAIT asserted
(RST-2) * E - TBD
ns
WRITES
28 t_{d(EMWEL-EMWAIT)}
Delay time from EM_WE low to EM_WAIT asserted
(WST-2) * E - TBD
ns
(1) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEW = Maximum
External Wait. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers.
(2) E = 6 x DSP period in ns for EMIFA. For example, when running the DSP CPU at 594 MHz, use E = 10.1 ns.
Table 5-31. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module⁽¹⁾⁽²⁾ (see Figure 5-17 and Figure 5-18)
NO.
1 t_{d(TURNAROUND)}
3 t_c(EMRCYCLE)
4 t_{su(EMCSL-EMOEL)}
5 t_{h(EMOEH-EMCSH)}
6 t_{su(EMBAV-EMOEL)}
7 t_{h(EMOEH-EMBAIV)}
8 t_{su(EMBAV-EMOEL)}
9 t_{h(EMOEH-EMBAIV)}
PARAMETER
READS and WRITES
Turn around time
READS
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 1)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 0)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[21:0] invalid
-594
MIN
UNIT
MAX
0
(TA + 1) * E ± TBD ns
3E ± TBD
3E ± TBD
E ± TBD
0
E ± TBD
0
E ± TBD
E ± TBD
E ± TBD
E ± TBD
92 * E ± TBD ns
4188 * E ± TBD ns
(RS + 1) * E ± TBD ns
ns
(RH + 1) * E ± TBD ns
ns
(RS + 1) * E ± TBD ns
(RH + 1) * E ± TBD ns
(RS + 1) * E ± TBD ns
(RH + 1) * E ± TBD ns
(1) RS = Read setup, RST = Read STrobe, RH = Read Hold, WS = Write Setup, WST = Write STrobe, WH = Write Hold, TA = Turn
Around, EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous Bank and
Asynchronous Wait Cycle Configuration Registers.
(2) E = 6 x DSP period in ns for EMIFA. For example, when running the DSP CPU at 594 MHz, use E = 10.1 ns.
122 Peripheral and Electrical Specifications