TMS320DM6443 Datasheet, PDF (101/202 Pages) Texas Instruments – Digital Media System on-Chip

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MPU
INTERRUPT
NUMBER
28
29
30
31
ACRONYM
DDRINT
EMIFAINT
VLQINT
TMS320DM6443
Digital Media System on-Chip
SPRS282 – DECEMBER 2005
Table 5-16. DM6443 MPU Interrupts (continued)
SOURCE
Reserved
DDR2 Memory Controller
EMIFA
VLYNQ
MPU
INTERRUPT
NUMBER
60
61
62
63
ACRONYM
GPIOBNK4
COMMTX
COMMRX
EMUINT
SOURCE
GPIO Bank 4
ARMSS
ARMSS
E2ICE
Table 5-17. ARM Interrupt Controller Registers
HEX ADDRESS
0x01C4 8000
0x01C4 8004
0x01C4 8008
0x01C4 800C
0x01C4 8010
0x01C4 8014
0x01C4 8018
0x01C4 801C
0x01C4 8020
0x01C4 8024
0x01C4 8028 - 0x01C4 802F
0x01C4 8030
0x01C4 8034
0x01C4 8038
0x01C4 803C
0x01C4 8040
0x01C4 8044
0x01C4 8048
0x01C4 804C
0x01C4 8050 - 0x01C4 83FF
ACRONYM
FIQ0
FIQ1
IRQ0
IRQ1
FIQENTRY
IRQENTRY
EINT0
EINT1
INCTL
EABASE
-
INTPRI0
INTPRI1
INTPRI2
INTPRI3
INTPRI4
INTPRI5
INTPRI6
INTPRI7
-
REGISTER DESCRIPTION
FIQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to
FIQ)]
FIQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to
FIQ)]
IRQ Interrupt Status 0 [Interrupt Status of INT[31:0] (If Mapped to
IRQ)]
IRQ Interrupt Status 1 [Interrupt Status of INT[63:32] (If Mapped to
IRQ)]
Entry Address [28:0] for Valid FIQ Interrupt
Entry Address [28:0] for Valid IRQ Interrupt
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Operation Control Register
Interrupt Entry Table Base Address Register
Reserved
Interrupt 0-7 Priority Select
Interrupt 8-15 Priority Select
Interrupt 16-23 Priority Select
Interrupt 24-31 Priority Select
Interrupt 32-39 Priority Select
Interrupt 40-47 Priority Select
Interrupt 48-55 Priority Select
Interrupt 56-63 Priority Select
Reserved
5.7.2 DSP Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 5-18. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts and the generation
of AEG events. Table 5-19 summarizes the C64x+ interrupt controller registers and memory locations. For
more details on DSP interrupt control, see the Documentation Support section for the DSP Subsystem
User's Guide.
Table 5-18. DM6443 DSP Interrupts
DSP
INTERRUPT
NUMBER
ACRONYM
0
EVT0
1
EVT1
2
EVT2
SOURCE
C64x+ Int Ctl 0
C64x+ Int Ctl 1
C64x+ Int Ctl 2
DSP
INTERRUPT
NUMBER
64
65
66
ACRONYM
SOURCE
Reserved
Reserved
Reserved
Peripheral and Electrical Specifications 101