AM1808_1112 Datasheet, PDF (181/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
www.ti.com
SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
Table 5-90. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 1848
0x01E0 184C
0x01E0 1850
0x01E0 1860
0x01E0 1868
0x01E0 186C
0x01E0 1870
0x01E0 2000
0x01E0 2800
0x01E0 2804
...
0x01E0 28FC
0x01E0 4000
0x01E0 4008
0x01E0 4020
0x01E0 4024
0x01E0 4028
0x01E0 402C
0x01E0 4080
0x01E0 4084
0x01E0 4088
0x01E0 4090
0x01E0 4094
0x01E0 5000
0x01E0 5004
0x01E0 5010
0x01E0 5014
...
0x01E0 50F0
0x01E0 50F4
0x01E0 600C
0x01E0 601C
...
0x01E0 63FC
0x01E0 6800
0x01E0 6804
0x01E0 6808
0x01E0 6810
0x01E0 6814
0x01E0 6818
...
0x01E0 6BF0
0x01E0 6BF4
0x01E0 6BF8
ACRONYM
RXGCR[2]
RXHPCRA[2]
RXHPCRB[2]
TXGCR[3]
RXGCR[3]
RXHPCRA[3]
RXHPCRB[3]
DMA_SCHED_CTRL
WORD[0]
WORD[1]
...
WORD[63]
QMGRREVID
DIVERSION
FDBSC0
FDBSC1
FDBSC2
FDBSC3
LRAM0BASE
LRAM0SIZE
LRAM1BASE
PEND0
PEND1
QMEMRBASE[0]
QMEMRCTRL[0]
QMEMRBASE[1]
QMEMRCTRL[1]
...
QMEMRBASE[15]
QMEMRCTRL[15]
CTRLD[0]
CTRLD[1]
...
CTRLD[63]
QSTATA[0]
QSTATB[0]
QSTATC[0]
QSTATA[1]
QSTATB[1]
QSTATC[1]
...
QSTATA[63]
QSTATB[63]
QSTATC[63]
REGISTER DESCRIPTION
Receive Channel 2 Global Configuration Register
Receive Channel 2 Host Packet Configuration Register A
Receive Channel 2 Host Packet Configuration Register B
Transmit Channel 3 Global Configuration Register
Receive Channel 3 Global Configuration Register
Receive Channel 3 Host Packet Configuration Register A
Receive Channel 3 Host Packet Configuration Register B
DMA Scheduler Control Register
DMA Scheduler Table Word 0
DMA Scheduler Table Word 1
...
DMA Scheduler Table Word 63
Queue Manager Registers
Queue Manager Revision Register
Queue Diversion Register
Free Descriptor/Buffer Starvation Count Register 0
Free Descriptor/Buffer Starvation Count Register 1
Free Descriptor/Buffer Starvation Count Register 2
Free Descriptor/Buffer Starvation Count Register 3
Linking RAM Region 0 Base Address Register
Linking RAM Region 0 Size Register
Linking RAM Region 1 Base Address Register
Queue Pending Register 0
Queue Pending Register 1
Memory Region 0 Base Address Register
Memory Region 0 Control Register
Memory Region 1 Base Address Register
Memory Region 1 Control Register
...
Memory Region 15 Base Address Register
Memory Region 15 Control Register
Queue Manager Queue 0 Control Register D
Queue Manager Queue 1 Control Register D
...
Queue Manager Queue 63 Status Register D
Queue Manager Queue 0 Status Register A
Queue Manager Queue 0 Status Register B
Queue Manager Queue 0 Status Register C
Queue Manager Queue 1 Status Register A
Queue Manager Queue 1 Status Register B
Queue Manager Queue 1 Status Register C
...
Queue Manager Queue 63 Status Register A
Queue Manager Queue 63 Status Register B
Queue Manager Queue 63 Status Register C
Copyright © 2010–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 181
Submit Documentation Feedback
Product Folder Link(s): AM1808