AM1808_1112 Datasheet, PDF (165/262 Pages) Texas Instruments – AM1808 ARM Microprocessor

AM1808
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SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011
Table 5-83. Additional⁽¹⁾ SPI1 Slave Timings, 5-Pin Option⁽²⁾⁽³⁾
NO.
PARAMETER
25 t_{d(SCSL_SPC)S}
Required delay from SPI1_SCS asserted at slave to
first SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
26 t_{d(SPC_SCSH)S}
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
27
t_{ena(SCSL_SOMI)}
S
Delay from master asserting SPI1_SCS to slave
driving SPI1_SOMI valid
28
t_{dis(SCSH_SOMI)S}
Delay from master deasserting SPI1_SCS to slave
3-stating SPI1_SOMI
29
t_{ena(SCSL_ENA)S}
Delay from master deasserting SPI1_SCS to slave
driving SPI1_ENA valid
Polarity = 0, Phase = 0,
from SPI1_CLK falling
30 t_{dis(SPC_ENA)S}
Delay from final clock
receive edge on SPI1_CLK
to slave 3-stating or driving
high SPI1_ENA.⁽⁴⁾
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
1.3V, 1.2V
MIN
MAX
P+1.5
1.1V
MIN
MAX
P+1.5
1.0V
MIN
MAX
P+1.5
UNIT
ns
0.5M+P+4
0.5M+P+5
0.5M+P+6
P+4
P+5
P+6
ns
0.5M+P+4
0.5M+P+5
0.5M+P+6
P+4
P+5
P+6
P+15
P+17
P+19
ns
P+15
P+17
P+19
ns
15
17
19
ns
2.5P+15
2.5P+17
2.5P+19
2.5P+15
2.5P+15
2.5P+17
2.5P+17
2.5P+19
ns
2.5P+19
2.5P+15
2.5P+17
2.5P+19
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-77).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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Peripheral Information and Electrical Specifications 165
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