TMS320DM355 Datasheet, PDF (18/153 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463 – SEPTEMBER 2007
www.ti.com
Table 2-8. Analog Video Terminal Functions
TERMINAL
NAME
NO.
TYPE⁽¹⁾ OTHER⁽²⁾ DESCRIPTION
VREF
IOUT
IBIAS
VFB
TVOUT
V_{DDA18_DAC}
V_{SSA_DAC}
J7
A I/O/Z
E1
A I/O/Z
F2
A I/O/Z
G1
A I/O/Z
F1
A I/O/Z
L7
PWR
L8
GND
Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not
used, the VREF signal should be connected to V_SS.
Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not
used, the IOUT signal should be connected to V_SS.
Video DAC: External resistor (2550 Ohms to GND) connection for current bias
configuration. When the DAC is not used, the IBIAS signal should be connected to
V_SS.
Video DAC: Pre video buffer DAC output (1000 Ohms to IOUT, 1070 Ohms to
TVOUT). When the DAC is not used, the VFB signal should be connected to V_SS.
Video DAC: Analog Composite NTSC/PAL output (SeeFigure 5-31 andFigure 5-32 for
V
circuit connection). When the DAC is not used, the TVOUT signal should be left as a
No Connect or connected to V_SS.
Video DAC: Analog 1.8V power. When the DAC is not used, the V_{DDA18_DAC} signal
should be connected to V_SS.
Video DAC: Analog 1.8V ground. When the DAC is not used, the V_{SSA_DAC} signal
should be connected to V_SS.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply
voltage for each signal. See Section 5.3, Power Supplies for more detail.
(2) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
2.4.3 Asynchronous External Memory Interface (AEMIF)
The Asynchronous External Memory Interface (AEMIF) signals support AEMIF, NAND, and OneNAND.
Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions
TERMINAL
NAME
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
EM_A13/
GIO067/
V19
BTSEL[1]
I/O/Z
Async EMIF: Address bus bit[13]
PD
GIO: GIO[67]
V_DD
System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used
to drive boot status LED signal (active low) in ROM boot modes.
EM_A12/
GIO066/
U19
BTSEL[0]
I/O/Z
PD
V_DD
Async EMIF: Address bus bit[12]
GIO: GIO[66]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
EM_A11/
GIO065/
R16
AECFG[3]
I/O/Z
Async EMIF: Address bus bit[11]
PU
GIO: GIO[65]
V_DD
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[3] sets
default for PinMux2_EM_D15_8: AEMIF default bus width (16 or 8 bits)
EM_A10/
GIO064/
R18
AECFG[2]
I/O/Z
Async EMIF: Address bus bit[10]
PU
V_DD
GIO: GIO[64]
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
EM_A09/
GIO063/
P17
AECFG[1]
I/O/Z
Async EMIF: Address bus bit[09]
PD
V_DD
GIO: GIO[63]
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
EM_A08/
GIO062/
T19
AECFG[0]
EM_A07/
GIO061
P16
I/O/Z
I/O/Z
Async EMIF: Address bus bit[08]
GIO: GIO[62]
PD
AECFG[0] sets default for:
V_DD
• PinMux2_EM_A0_BA1: AEMIF address width (OneNAND or NAND)
• PinMux2_EM_A13_3: AEMIF address width (OneNAND or NAND)
V_DD
Async EMIF: Address bus bit[07]
GIO: GIO[61]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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