TMS320DM355 Datasheet, PDF (135/153 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

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5.13.1 I2C Electrical Data/Timing
5.13.1.1 Inter-Integrated Circuits (I2C) Timing
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463 – SEPTEMBER 2007
Table 5-33. Timing Requirements for I2C Timings⁽¹⁾ (see Figure 5-39)
DM355
NO.
STANDARD
MODE
FAST MODE
UNIT
MIN MAX
MIN MAX
1
t_c(SCL)
Cycle time, SCL
10
2
t_{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
2.5
μs
0.6
μs
3
t_h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
μs
4
t_w(SCLL)
Pulse duration, SCL low
5
t_w(SCLH)
Pulse duration, SCL high
6 t_{su(SDAV-SCLH)} Setup time, SDA valid before SCL high
7
t_h(SDA-SCLL)
Hold time, SDA valid after SCL low (For I²C bus™ devices)
8
t_w(SDAH)
Pulse duration, SDA high between STOP and START
conditions
9
t_r(SDA)
Rise time, SDA
10
t_r(SCL)
Rise time, SCL
11
t_f(SDA)
Fall time, SDA
12
t_f(SCL)
Fall time, SCL
13 t_{su(SCLH-SDAH)} Setup time, SCL high before SDA high (for STOP condition)
14 t_w(SP)
15
C_b ⁽⁵⁾
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4.7
1.3
μs
4
0.6
μs
250
100 ⁽²⁾
ns
0 ⁽³⁾
0⁽³⁾ 0.9 ⁽⁴⁾ μs
4.7
1.3
1000
1000
300
300
20 + 0.1C_b(5)
20 + 0.1C_b(5)
20 + 0.1C_b(5)
20 + 0.1C_b(5)
4
0.6
0
400
μs
300 ns
300 ns
300 ns
300 ns
μs
50 ns
400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus™ system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
(5) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
8
4
10
6
5
14
13
SCL
1
12
3
7
2
3
Stop Start
Repeated
Start
Stop
Figure 5-39. I2C Receive Timings
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Peripheral Information and Electrical Specifications 135