TMS320DM355 Datasheet, PDF (138/153 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463 – SEPTEMBER 2007
5.14.1 ASP Electrical Data/Timing
5.14.1.1 Audio Serial Port (ASP) Timing
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Table 5-35. Timing Requirements for ASP⁽¹⁾ (see Figure 5-41)
NO.
15 tc(CLK)
16 OTG(CLKS)
5
t_su(FRH-CKRL)
6
t_h(CKRL-FRH)
7
t_su(DRV-CKRL)
8
t_h(CKRL-DRV)
10 t_su(FXH-CKXL)
11 t_h(CKXL-FXH)
Cycle time, CLK
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLK ext
CLKS ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
DM355
MIN
38.5 or 2P⁽²⁾⁽³⁾
19.25 or P^{(2) (3) (4)}
21
6
0
6
21
6
0
6
21
6
0
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .
(3) Use which ever value is greater.
(4) The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.
138 Peripheral Information and Electrical Specifications
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