TLC3544 Datasheet, PDF (18/40 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
detailed description (continued)
command period
After the rising edge of FS (FS triggers the operation) or the falling edge of CS (CS triggers the operation), SDI,
SDO, and SCLK are enabled. The first four SCLK clocks form the command period. The four MSBs of input data,
ID[15:12], are shifted in and decoded. These bits represent one of the 4-bit commands from the host, which
defines the required operation (see Table 1, Command Set). The four MSBs of output, OD[15:12], are also
shifted out via SDO during this period.
The commands are SELECT/CONVERSION, WRITE CFR, FIFO READ, SW POWER DOWN, and
HARDWARE DEFAULT mode. The SELECT/CONVERSION command includes SELECT ANALOG INPUT
and SELECT TEST commands. All cause a select/conversion operation. They select the analog signal being
converted, and start the sampling/conversion process after the selection. WRITE CFR causes the configuration
operation, which writes the device configuration information into the CFR register. FIFO READ reads the
contents in the FIFO. SW POWER DOWN puts the device into software power-down mode to save power.
Hardware default mode sets the device into the hardware default mode.
After the command period, the remaining 12 bits of SDI are written into the CFR register to configure the device
if the command is WRITE CFR. Otherwise, these bits are ignored. The configuration is retained in the
autopower-down and software power-down state. If SCLK stops (while CS remains low) after the first eight bits
are entered, the next eight bits can be entered after SCLK resumes. The data on SDI are ignored after the 4-bit
counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.
The remaining 12 bits of output data are shifted out from SDO if the command is SELECT/CONVERSION or
FIFO READ. Otherwise, the data on SDO are ignored. In any case, SDO goes into a high-impedance state after
the 4-bit counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.
Table 1. Command Set (CMR)
SDI Bit D[15:12]
BINARY HEX
TLC3548 COMMAND
TLC3544 COMMAND
0000b
0h SELECT analog input channel 0
SELECT analog input channel 0
0001b
1h SELECT analog input channel 1
SELECT analog input channel 1
0010b
2h SELECT analog input channel 2
SELECT analog input channel 2
0011b
3h SELECT analog input channel 3
SELECT analog input channel 3
0100b
4h SELECT analog input channel 4
SELECT analog input channel 0
0101b
5h SELECT analog input channel 5
SELECT analog input channel 1
0110b
6h SELECT analog input channel 6
SELECT analog input channel 2
0111b
7h SELECT analog input channel 7
SELECT analog input channel 3
1000b
8h SW POWER DOWN
1001b
9h Reserved (test)
1010b
Ah WRITE CFR, the last 12 bits of SDI are written into CFR. This command resets FIFO.
1011b
Bh SELECT TEST, voltage = (REFP+REFM)/2 (see Notes 9 and 10)
1100b
Ch SELECT TEST, voltage = REFM (see Note 11)
1101b
Dh SELECT TEST, voltage = REFP (see Note 12)
1110b
Eh FIFO READ, FIFO contents is shown on SDO; OD[15:2] = result, OD[1:0] = xx
1111b
Fh Hardware default mode, CFR is loaded with 800h
NOTES: 9. REFP is external reference if external reference is selected, or internal reference if internal reference
is programmed.
10. The output code = mid-scale code + zero offset error + gain error.
11. The output code = zero scale code + zero offset error.
12. The output code = full-scale code + gain error.
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