TLC3544 Datasheet, PDF (11/40 Pages) Texas Instruments – 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
timing requirements over recommended operating free-air temperature range, AV_DD = 5 V,
DV_DD = 5 V, V_REFP = 5 V, V_REFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CS trigger
PARAMETERS
tsu(2) Setup time, CS falling edge before SCLK rising edge, at 25-pF load
td(4) Delay time, delay time from 16th SCLK falling edge to CS rising edge, at 25-pF load ^‡
tw(2) Pulse width, CS high time at 25-pF load
td(5)
Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%
final level), at 10-pF load
DVDD = 5 V
DVDD = 2.7 V
td(6) Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load
td(7) Delay time, delay from CS falling edge to INT rising edge, at 10-pF load
DVDD = 5 V
DVDD = 2.7 V
† _{Specified by design}
‡ _{For normal short sampling, td(4) is the delay time from 16th SCLK falling edge to CS rising edge.}
For normal long sampling, td(4) is the delay time from 48th SCLK falling edge to CS rising edge.
MIN TYP
12
5
1
0
0
0
0
0
MAX
12
30^†
6
6
16^†
UNIT
ns
ns
tc(1)
ns
ns
ns
CS
VIH
VIL
tsu(2)
td(4)
tw(2)
SCLK
1
16
SDI
SDO
Don’t Care
td(5)
Hi-Z
ID15 ID1
ID0
OD15 OD1 OD0
Don’t Care
Hi-Z
Don’t Care
OD15
td(6)
OD7 ^Hi-Z
EOC
OR
INT
td(7)
NOTE A: – – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored. Parts with date code earlier than 13XXXXX have these discrepancies:
(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,
in this case, is 2001 and the month of March.)
FS is not ignored even if the device is in microcontroller mode (CS triggered).
FS must be tied to DVDD.
Figure 2. Critical Timing for CS Trigger
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