AM3359_12 Datasheet, PDF (172/195 Pages) Texas Instruments – AM335x ARM® Cortex™-A8 Microprocessors (MPUs)

AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717B – OCTOBER 2011 – REVISED JANUARY 2012
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5.5 LCD Controller (LCDC)
The LCD controller consists of two independent controllers, the raster controller and the LCD interface
display driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
• The raster controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the raster engine which, in turn,
outputs to the external LCD device.
• The LIDD controller supports the asynchronous LCD interface. It provides full-timing programmability of
control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 2048 x 2048 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate.
Table 5-61. LCD Controller Timing Conditions
TIMING CONDITION PARAMETER
Output Condition
C_LOAD
Output load capacitance
LIDD mode
Raster mode
MIN TYP
5
3
MAX UNIT
60 pF
30 pF
5.5.1 LCD Interface Display Driver (LIDD Mode)
Table 5-62. Timing Requirements for LCD LIDD Mode
(see Figure 5-63 through Figure 5-71)
NO.
PARAMETER
16
t_{su(LCD_DATA-LCD_MEMORY_CLK)}
17
t_{h(LCD_MEMORY_CLK-LCD_DATA)}
18
t_{t(LCD_DATA)}
Setup time, LCD_DATA[15:0] valid before
LCD_MEMORY_CLK high
Hold time, LCD_DATA[15:0] valid after
LCD_MEMORY_CLK high
Transition time, LCD_DATA[15:0]
OPP100
MIN
18
UNIT
MAX
ns
0
ns
1
3 pf
Table 5-63. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode
(see Figure 5-63 through Figure 5-71)
NO.
PARAMETER
OPP100
UNIT
MIN
MAX
1
t_{c(LCD_MEMORY_CLK)}
2
t_{w(LCD_MEMORY_CLKH)}
3
t_{w(LCD_MEMORY_CLKL)}
4
t_{d(LCD_MEMORY_CLK-LCD_DATAV)}
Cycle time, LCD_MEMORY_CLK
Pulse duration, LCD_MEMORY_CLK high
Pulse duration, LCD_MEMORY_CLK low
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] valid (write)
23.7
0.45t_c
0.45t_c
ns
0.55t_c ns
0.55t_c ns
7 ns
5
t_{d(LCD_MEMORY_CLK-LCD_DATAI)}
Delay time, LCD_MEMORY_CLK high to
LCD_DATA[15:0] invalid (write)
0
ns
6
t_{d(LCD_MEMORY_CLK-LCD_AC_BIAS_EN)}
Delay time, LCD_MEMORY_CLK high to
LCD_AC_BIAS_EN
0
6.8 ns
7
t_{t(LCD_AC_BIAS_EN)}
8
t_{d(LCD_MEMORY_CLK-LCD_VSYNC)}
Transition time, LCD_AC_BIAS_EN
Delay time, LCD_MEMORY_CLK high to
LCD_VSYNC
1
10 ns
0
7 ns
9
t_{t(LCD_VSYNC)}
10
t_{d(LCD_MEMORY_CLK-LCD_HYSNC)}
Transition time, LCD_VSYNC
Delay time, LCD_MEMORY_CLK high to
LCD_HSYNC
1
10 ns
0
7 ns
172 Peripheral Information and Timings
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