TMS320C6745 Datasheet, PDF (166/209 Pages) Texas Instruments – Floating-point Digital Signal Processor

TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377A – SEPTEMBER 2008 – REVISED OCTOBER 2008
www.ti.com
6.22 LCD Controller
Table 6-74 lists the LCD Controller registers
Table 6-74. LCD Controller (LCDC) Registers
Address Offset
0x01E1 3000
0x01E1 3004
0x01E1 3008
0x01E1 300C
0x01E1 3010
0x01E1 3014
0x01E1 3018
0x01E1 301C
0x01E1 3020
0x01E1 3024
0x01E1 3028
0x01E1 302C
0x01E1 3030
0x01E1 3034
0x01E1 3038
0x01E1 3040
0x01E1 3044
0x01E1 3048
0x01E1 304C
0x01E1 3050
Acronym
REVID
LCD_CTRL
LCD_STAT
LIDD_CTRL
LIDD_CS0_CONF
LIDD_CS0_ADDR
LIDD_CS0_DATA
LIDD_CS1_CONF
LIDD_CS1_ADDR
LIDD_CS1_DATA
RASTER_CTRL
RASTER_TIMING_0
RASTER_TIMING_1
RASTER_TIMING_2
RASTER_SUBPANEL
LCDDMA_CTRL
LCDDMA_FB0_BASE
LCDDMA_FB0_CEILING
LCDDMA_FB1_BASE
LCDDMA_FB1_CEILING
Register Description
LCD Revision Identification Register
LCD Control Register
LCD Status Register
LCD LIDD Control Register
LCD LIDD CS0 Configuration Register
LCD LIDD CS0 Address Read/Write Register
LCD LIDD CS0 Data Read/Write Register
LCD LIDD CS1 Configuration Register
LCD LIDD CS1 Address Read/Write Register
LCD LIDD CS1 Data Read/Write Register
LCD Raster Control Register
LCD Raster Timing 0 Register
LCD Raster Timing 1 Register
LCD Raster Timing 2 Register
LCD Raster Subpanel Display Register
LCD DMA Control Register
LCD DMA Frame Buffer 0 Base Address Register
LCD DMA Frame Buffer 0 Ceiling Address Register
LCD DMA Frame Buffer 1 Base Address Register
LCD DMA Frame Buffer 1 Ceiling Address Register
6.22.1 LCD Interface Display Driver (LIDD Mode)
NO
16
t_{su(LCD_D)}
17
t_{h(LCD_D)}
Table 6-75. LCD LIDD Mode Timing Requirements
PARAMETER
MIN
Setup time, LCD_D[15:0] valid
before LCD_MCLK ↑
7
Hold time, LCD_D[15:0] valid after
LCD_MCLK ↑
0
MAX
NO PARAMETER
4
t_{d(LCD_D_V)}
5
t_{d(LCD_D_I)}
6
t_{d(LCD_E_A})
7
t_{d(LCD_E_I)}
8
t_{d(LCD_A_A)}
9
t_{d(LCD_A_I)}
10
t_{d(LCD_W_A)}
Table 6-76. LCD LIDD Mode Timing Characteristics
MIN
Delay time, LCD_MCLK ↑ to
LCD_D[15:0] valid (write)
0
Delay time, LCD_MCLK ↑ to
LCD_D[15:0] invalid (write)
0
Delay time, LCD_MCLK ↑ to
LCD_AC_ENB_CS↓
0
Delay time, LCD_MCLK ↑ to
LCD_AC_ENB_CS↑
0
Delay time, LCD_MCLK ↑ to
LCD_VSYNC↓
0
Delay time, LCD_MCLK ↑ to
LCD_VSYNC↑
0
Delay time, LCD_MCLK ↑ to
LCD_HSYNC↓
0
MAX
7
7
7
7
7
7
7
UNIT
ns
ns
UNIT
ns
ns
ns
ns
ns
ns
ns
166 Peripheral Information and Electrical Specifications
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