LP3878-ADJ_15 Datasheet, PDF (16/25 Pages) Texas Instruments – Micropower 800-mA Low-Noise

LP3878-ADJ
SNVS311D – MAY 2005 – REVISED FEBRUARY 2015
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• For V_OUT > 2.5 V: C_FF should be selected to set the zero frequency in the range of about 20 kHz to 100 kHz.
8.2.2.3 Capacitor Characteristics
8.2.2.3.1 Ceramic
The LP3878-ADJ was designed to work with ceramic capacitors on the output to take advantage of the benefits
they offer: for capacitance values in the 10-µF range, ceramics are the least expensive and also have the lowest
ESR values (which makes them best for eliminating high-frequency noise). The ESR of a typical 10-µF ceramic
capacitor is in the range of 5 mΩ to 10 mΩ, which meets the ESR limits required for stability by the LP3878-ADJ.
One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Many large value
ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in
the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.
Another significant problem with Z5U and Y5V dielectric devices is that the capacitance drops severely with
applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated
voltage applied to it.
For these reasons, X7R and X5R type ceramic capacitors must be used on the input and output of the LP3878-
ADJ.
8.2.2.4 Setting the Output Voltage
The output voltage is set using resistors R1 and R2 (see Figure 27).
The formula for output voltage is:
V_OUT = V_ADJ × (1 + (R1 / R2))
(3)
R2 must be less than 5 kΩ to ensure loop stability.
To prevent voltage errors, R1 and R2 must be located near the LP3878-ADJ and connected via traces with no
other currents flowing in them (Kelvin connect). The bottom of the R1/R2 divider must be connected directly to
the LP3878-ADJ ground pin.
8.2.3 Application Curves
Figure 29. Load Transient Response
Figure 30. Load Transient Response
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