LP3878-ADJ_15 Datasheet, PDF (15/25 Pages) Texas Instruments – Micropower 800-mA Low-Noise

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LP3878-ADJ
SNVS311D – MAY 2005 – REVISED FEBRUARY 2015
NOTE
Important: The output capacitor must maintain its ESR within the stable region over the
full operating temperature range of the application to assure stability.
The output capacitor ESR forms a zero which is required to add phase lead near the loop gain crossover
frequency, typically in the range of 50 kHz to 200 kHz. The ESR at lower frequencies is of no importance. Some
capacitor manufacturers list ESR at low frequencies only, and some give a formula for Dissipation Factor (DF)
which can be used to calculate a value for a term referred to as ESR. However, because the DF formula is
usually at a much lower frequency than the range listed above, it will give an unrealistically high value. If good
quality X5R or X7R ceramic capacitors are used, the actual ESR in the 50-kHz to 200-kHz range will not exceed
25 mΩ. If these are used as output capacitors for the LP3878-ADJ, the regulator stability requirements are
satisfied.
It is important to remember that capacitor tolerance and variation with temperature must be taken into
consideration when selecting an output capacitor so that the minimum required amount of output capacitance is
provided over the full operating temperature range (see Capacitor Characteristics).
The output capacitor must be located not more than 0.5 inches from the OUT pin and returned to a clean analog
ground.
8.2.2.1.3 Noise Bypass Capacitor
The 10-nF capacitor on the BYPASS pin significantly reduces noise on the regulator output and is required for
loop stability. However, the capacitor is connected directly to a high-impedance circuit in the bandgap reference.
Because this circuit has only a few µA flowing in it, any significant loading on this node will cause a change in the
regulated output voltage. For this reason, dc leakage current through the noise bypass capacitor must never
exceed 100 nA, and should be kept as low as possible for best output voltage accuracy.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic
capacitors with either NPO or COG dielectric typically have very low leakage. 10-nF polypropylene and
polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low
leakage current.
While the capacitor value on the BYPASS will affect start-up time, this is not intended to be used as a soft-start
circuit. There is no dedicated discharge circuitry for this capacitor, and it can be pre-biased if the IN pin, or the
SHUTDOWN pin are not at 0 V at start-up.
8.2.2.2 Feedforward Capacitor
The feedforward capacitor designated C_FF in Figure 27 is required to increase phase margin and assure loop
stability. Improved phase margin also gives better transient response to changes in load or input voltage, and
faster settling time on the output voltage when transients occur. C_FF forms both a pole and zero in the loop gain,
the zero providing beneficial phase lead (which increases phase margin) and the pole adding undesirable phase
lag (which should be minimized). The zero frequency is determined both by the value of C_FF and R1:
f_Z = 1 / (2πC_FF × R1)
(1)
The pole frequency resulting from C_FF is determined by the value of C_FF and the parallel combination of R1 and
R2:
f_P = 1 / (2πC_FF × (R1 // R2))
(2)
At higher output voltages where R1 is much greater than R2, the value of R2 primarily determines the value of
the parallel combination of R1 // R2. This puts the pole at a much higher frequency than the zero. As the
regulated output voltage is reduced (and the value of R1 decreases), the parallel effect of R2 diminishes and the
two equations become equal (at which point the pole and zero cancel out). Because the pole frequency gets
closer to the zero at lower output voltages, the beneficial effects of C_FF are increased if the frequency range of
the zero is shifted slightly higher for applications with low V_OUT (because then the pole adds less phase lag at the
loop crossover frequency).
C_FF should be selected to place the pole-zero pair at a frequency where the net phase lead added to the loop at
the crossover frequency is maximized. The following design guidelines were obtained from bench testing to
optimize phase margin, transient response, and settling time:
• For V_OUT ≤ 2.5 V: C_FF should be selected to set the zero frequency in the range of about 50 kHz to 200 kHz.
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