DAC8541 Datasheet, PDF (16/21 Pages) Texas Instruments – 16-BIT SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG CONVERTER WITH RAIL VOLTAGE OUTPUT

DAC8541
SLAS353 − DECEMBER 2001
THEORY OF OPERATION
power-down modes
The DAC8541 utilizes four modes of operation. These modes are programmable via two inputs (PD1 and PD0)
to the device. Table 3 shows how the state of these pins correspond to the mode of operation of the DAC8541.
Table 3. Modes of Operation for the DAC8541
PD1
PD0
OPERATING MODE
0
0
Normal operation
POWER-DOWN MODES
0
1
1 kΩ to AGND
1
0
100 kΩ to AGND
1
1
High impedance
When both pins are set to 0, the device works normally with its typical power consumption of 250 µA at
AV_DD = 5 V. However, for the three power-down modes, the supply current falls to 200 nA at AV_DD = 5 V (50 nA
at AV_DD = 3 V). Not only does the supply current fall, but the V_OUT terminal is internally switched from the output
of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the
device is known while in power-down mode. There are three different options: The output is connected internally
to AGND through a 1-kΩ resistor, it is connected to AGND through a 100-kΩ resistor, or it is left open-circuited
(high impedance). The output stage is illustrated in Figure 31.
DAC
Amplifier
_
+
VOUTSense
VOUT
Powerdown
Circuitry
Resistor
Network
Figure 31. Output Stage During Power Down (High-Impedance)
All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. This allows the DAC’s output voltage to return to the previous level
when power-up resumes. The delay time required to exit power-down is typically 2.5 µs for AV_DD = 5 V and 5
µs for AV_DD = 3 V. (See the typical curves section for additional information.)
voltage reference inputs
Two voltage inputs provide the reference set points for the DAC architecture. These are V_REFH and V_REFL. For
typical rail-to-rail operation, V_REFH should be equivalent to AV_DD and V_REFL tied to AGND. The output voltage
is given by:
VOUT + VREFH * 2 VREFL
The use of the V_REFL input allows minor adjustments to be made to the offset of the DAC output by applying
a small voltage to the V_REFL input. The acceptable range is between −100 mV and 100 mV with respect to
AGND. A low output impedance source is needed, so that the accuracy of the DAC over its operating range is
not affected.
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