DAC8541 Datasheet, PDF (15/21 Pages) Texas Instruments – 16-BIT SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG CONVERTER WITH RAIL VOLTAGE OUTPUT

DAC8541
THEORY OF OPERATION
SLAS353 − DECEMBER 2001
data format
Table 2 details the input data format of the DAC8541. Two data I/O formats are available to the host interface.
These two formats are binary 2s complement (BTC) and unipolar straight binary (USB). The BTC/USB input
pin controls the format used by the DAC. The data format selected by the BTC/USB input is used for data written
into the device as well as data that is read back from the DAC8541. (Refer to Table 1 and Figure 1 for additional
information for performing read and write operations.)
Table 2. DAC8541 Data Format
BTC/USB = 0
UNIPOLAR STRAIGHT BINARY
DIGITAL INPUT
ANALOG OUTPUT
0x0000h
Min-scale
0x0001h
Min-scale + 1 LSB
S
S
S
S
0x8000h
Mid-scale
0x8001h
Mid-scale + 1 LSB
S
S
S
S
0xFFFFh
Full Scale
BTC/USB = 1
BINARY 2s COMPLEMENT
DIGITAL INPUT
ANALOG OUTPUT
0x8000h
Min-scale
0x8001h
Min-scale + 1 LSB
S
S
S
S
0x0000h
Mid-scale
0x0001h
Mid-scale + 1 LSB
S
S
S
S
0x7FFFh
Full Scale
LDAC function
The DAC8541 is designed using a double-buffered architecture. A write command transfers data from the data
input pins into the input register. The data is held in the input register until a rising edge is detected on the LDAC
input. This rising edge signal transfers the data from the input register to the DAC register. Upon issuance of
the rising LDAC edge, the output of the DAC8541 begins settling to the newly written data value presented to
the DAC register.(Data in the input register is not changed when an LDAC command is given.)
RST and RSTSEL
The RST and RSTSEL inputs control the reset of the DAC register and consequently, the DAC output. The reset
command is edge triggered by a low-to-high transition on the RST pin. Once a rising edge on RST is detected,
the DAC output may settle to the mid-scale or min-scale code depending on the state of the RSTSEL input. A
logic high value on RSTSEL causes the DAC output to reset to mid-scale and a logic low value resets the DAC
to min-scale. Application of a valid reset signal to the DAC does not overwrite existing data in the input register.
power-on reset
The DAC8541 contains a power-on reset circuit that controls the output voltage during power up. On power up,
the DAC register (and DAC output) is set to min-scale (plus a small offset error produced by the output buffer).
It remains at min-scale until a valid write sequence is made to the DAC changing the DAC register data. This
is useful in applications where it is important to know the state of the output of the DAC while the system is in
the process of powering up. DGND must be applied to all digital inputs until the digital and analog supplies are
applied to the DAC8541. Logic voltages applied to the input pins when power is not applied to DV_DD and AV_DD,
may power the device through the ESD input structures causing undesired operation.
www.ti.com
15