BUF602IDBVTG4 Datasheet, PDF (16/27 Pages) Texas Instruments – High-Speed, Closed-Loop Buffer

BUF602
SBOS339B – OCTOBER 2005 – REVISED MAY 2008 ...................................................................................................................................................... www.ti.com
across the part. P_DL will depend on the required
output signal and load but would, for a grounded
resistive load, be at a maximum when the output is
fixed at a voltage equal to 1/2 of either supply voltage
(for equal bipolar supplies). Under this condition, P_DL
= V_S2/(4 × R_L).
Note that it is the power in the output stage and not
into the load that determines internal power
dissipation.
As a worst-case example, compute the maximum T_J
using a BUF602IDBV in the circuit on the front page
operating at the maximum specified ambient
temperature of +85°C and driving a grounded 20Ω
load.
P_D = 10V × 5.8mA + 5²/(4 × 20Ω) = 370.5mW
Maximum T_J = +85°C + (0.37W × 150°C/W) = 141°C.
Although this is still below the specified maximum
junction temperature, system reliability considerations
may require lower tested junction temperatures. The
highest possible internal dissipation will occur if the
load requires current to be forced into the output for
positive output voltages or sourced from the output
for negative output voltages. This puts a high current
through a large internal voltage drop in the output
transistors. The output V-I plot (Figure 16) shown in
the Typical Characteristics include a boundary for 1W
maximum internal power dissipation under these
conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a
high-frequency amplifier like the BUF602 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC ground
for all of the signal I/O pins. Parasitic capacitance on
the output pins can cause instability: on the
noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To
reduce unwanted capacitance, a window around the
signal I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
b) Minimize the distance (< 0.25") from the
power-supply pins to high-frequency 0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor (0.1µF) across the two power
supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the BUF602. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal film
or carbon composition, axially-leaded resistors can
also provide good high-frequency performance.
Again, keep their leads and PCB traces as short as
possible. Never use wirewound type resistors in a
high-frequency application.
d) Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. If a long trace is required, and the 6dB
signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook
for microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary on board, and
in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots.
e) Socketing a high-speed part like the BUF602 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
that makes it almost impossible to achieve a smooth,
stable frequency response. Best results are obtained
by soldering the BUF602 onto the board.
16
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