ADS62C17_1 Datasheet, PDF (16/67 Pages) Texas Instruments – Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost

ADS62C17
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
A) Enable serial readout (<SERIAL READOUT> = 1)
REGISTER ADDRESS (A7:A0) = 0x00
REGISTER DATA (D7:D0) = 0x01
SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
SDOUT
Pin SDOUT is NOT in high-impedance state; it is forced low by the device (<SERIAL READOUT> = 0)
B) Read contents of register 0x3F.
This register has been initialized with 0x04
(device is put in global power down mode)
REGISTER ADDRESS (A7:A0) = 0x3F
REGISTER DATA (D7:D0 ) = XX (don’t care)
SDATA
SCLK
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SEN
SDOUT
0
0
0
0
Pin SDOUT functions as serial readout (<SERIAL READOUT> = 1)
0
1
0
0
Figure 8. Serial Readout
RESET TIMING (WHEN USING SERIAL INTERFACE ONLY)
Typical values at 25°C, min and max values across the full temperature range T_MIN = –40°C to T_MAX = 85°C, unless otherwise
noted.
PARAMETER
t₁ Power-on delay
t₂ Reset pulse width
t₃ Register write delay
CONDITIONS
Delay from power-up of AVDD and DRVDD to RESET pulse active
Pulse width of active RESET signal
Delay from RESET disable to SEN active
MIN TYP
1
10
100
MAX
1 ⁽¹⁾
UNIT
ns
ns
µs
ns
(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1usec, the device could
enter the parallel configuration mode briefly and then return back to serial interface mode.
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