ADS62C17_1 Datasheet, PDF (13/67 Pages) Texas Instruments – Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost

ADS62C17
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
SERIAL INTERFACE CONFIGURATION ONLY
To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to be
kept low.
SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internal
registers of the ADC.
The registers can be reset either by applying a pulse on RESET pin or by setting the <RESET> bit high. The
serial interface section describes the register programming and register reset in more detail.
USING BOTH SERIAL INTERFACE and PARALLEL CONTROLLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins
CTRL1 to CTRL3 are available. After power-up, the device will automatically get configured as per the voltage
settings on these pins (Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used to
access the internal registers of ADC. The registers must first be reset to their default values either by applying a
pulse on RESET pin or by setting bit <RST> = 1. After reset, the RESET pin must be kept low. The serial
interface section describes the register programming and register reset in more detail.
DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 6.
SCLK
0
+200mV/-0mV
(3/8)AVDD
±200mV
(5/8)2AVDD
±200mV
AVDD
+0mV/-200mV
Table 5. SCLK Control Pin
DESCRIPTION
Internal reference
External reference
External reference
Internal reference
SEN
0
+200mV/-0mV
(3/8)AVDD
±200mV
(5/8)2AVDD
±200mV
AVDD
+0mV/-200mV
Table 6. SEN Control Pin
DESCRIPTION
Offset binary and DDR LVDS output
2’s complement format and DDR LVDS output
2’s complement format and parallel CMOS output
Offset binary and parallel CMOS output
CTRL1
LOW
LOW
LOW
LOW
HIGH
HIGH
CTRL2
LOW
LOW
HIGH
HIGH
LOW
LOW
Table 7. CTRL1, CTRL2 and CTRL3 Pins
CTRL3
LOW
HIGH
LOW
HIGH
LOW
HIGH
DESCRIPTION
Normal operation
SNRBoost enabled for Channel B⁽¹⁾
SNRBoost enabled for Channel A⁽¹⁾
SNRBoost enabled for Channel A and B⁽¹⁾
Global power down
Channel B standby
(1) To enable & disable SNRBoost mode using the CTRL pins, reset the register bits <SNRBoost Enable -
CHA> = 0 & <SNRBoost Enable - CHB> = 0.
Copyright © 2009, Texas Instruments Incorporated
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