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ADS5287 Datasheet, PDF (16/31 Pages) Texas Instruments – 10-Bit, Octal-Channel ADC Up to 65MSPS
ADS5287
SBAS428 – JANUARY 2008
www.ti.com
DESCRIPTION OF SERIAL REGISTERS
SOFTWARE RESET
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
00
X
NAME
RST
Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears
to '0'.
POWER-DOWN MODES
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
X
0F
0
X
X
0
NAME
PDN_CH<8:1>
PDN_PARTIAL
PDN_COMPLETE
PDN_PIN_CFG
Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for
the ADC channel <N>.
In addition to channel-specific power-down, the ADS5287 also has two global power-down modes—partial
power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip;
recovery from this mode is much quicker, provided that the clock has been running for at least 50µs before
exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and
involves a much longer recovery time.
In addition to programming the device for either of these two power-down modes (through either the
PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial
power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the
PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin
is high, the device enters partial power-down mode.
LVDS DRIVE PROGRAMMABILITY
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
11
X
X
X
X
X
X
NAME
ILVDS_LCLK<2:0>
ILVDS_FRAME<2:0>
ILVDS_DAT<2:0>
The LVDS drive strength of the bit clock (LCLKP or LCLKN) and the frame clock (ADCLKP or ADCLKN) can be
individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTN can also be
programmed to the same value.
16
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