ADS5287 Datasheet, PDF (15/31 Pages) Texas Instruments – 10-Bit, Octal-Channel ADC Up to 65MSPS

ADS5287
www.ti.com
SBAS428 – JANUARY 2008
Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (continued)
ADDRESS
IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
DESCRIPTION
DEFAULT
1
X
DIFF_CLK
Differential clock mode.
Single-
ended clock
1
X
EN_DCC
Enables the duty-cycle correction
circuit.
Disabled
42
1
1
X
XX
EXT_REF_VCM
Drives the external reference
mode through the V_CM pin.
PHASE_DDR<1:0>
Controls the phase of LCLK
output relative to data.
External
reference
drives REF_T
and REF_B
90 degrees
0 X PAT_DESKEW Enables deskew pattern mode.
Inactive
45
X0
PAT_SYNC
Enables sync pattern mode.
Inactive
1
1
X
BTC_MODE
Binary two's complement format
Straight
for ADC output.
offset binary
1
1
X
MSB_FIRST
Serialized ADC output comes
out MSB-first.
LSB-first
output
46
1
1
X
EN_SDR
Enables SDR output mode
(LCLK becomes a 12x input
clock).
DDR output
mode
1
X
1
1
FALL_SDR
Controls whether the LCLK rising
or falling edge comes in the
middle of the data window when
operating in SDR output mode.
Rising edge
of LCLK in
middle of
data window
SUMMARY OF FEATURES
FEATURES
ANALOG FEATURES
Internal or external reference
(driven on the REF_T and REF_B pins)
External reference driven on the V_CM pin
Duty cycle correction circuit
Low-frequency noise suppression
Single-ended or differential clock
Power-down mode
DIGITAL FEATURES
Programmable digital gain (0dB to 12dB)
Straight offset or BTC output
Swap polarity of analog input pins
LVDS OUTPUT PHYSICAL LAYER
LVDS internal termination
LVDS current programmability
LVDS OUTPUT TIMING
LSB- or MSB-first output
DDR or SDR output
LCLK phase relative to data output
DEFAULT
N/A
Off
Off
Off
Single-ended
Off
0dB
Straight offset
Off
Off
3.5mA
LSB-first
DDR
Refer to Figure 1
SELECTION
POWER IMPACT (relative to default)
AT f_S = 65MSPS
Pin
Register 42
Register 42
Register 14
Register 42
Pin and register 0F
Internal reference mode takes approximately 23mW more power on
AVDD
Approximately 9mW less power on AVDD
Approximately 7mW more power on AVDD
With zero input to the ADC, low-frequency noise suppression causes
digital switching at f_S/2, thereby increasing LVDD power by
approximately 7mW/channel
Differential clock mode takes approximately 7mW more power on
AVDD
Refer to the Power-Down Modes section in the Electrical
Characteristics table
Registers 2A and 2B
Register 46
Register 24
No difference
No difference
No difference
Register 12
Register 11
Approximately 7mW more power on AVDD
As per LVDS clock and data buffer current setting
Register 46
Register 46
Register 42
No difference
SDR mode takes approximately 2mW more power on LVDD
(at f_S = 30MSPS)
No difference
Copyright © 2008, Texas Instruments Incorporated
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