AMC1203_15 Datasheet, PDF (15/29 Pages) Texas Instruments – 1-Bit, 10MHz, 2nd-Order, Isolated Delta-Sigma Modulator

AMC1203
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DIGITAL OUTPUT
A differential input signal of 0V ideally produces a
stream of ones and zeros that are high 50% of the
time and low 50% of the time. A differential input of
+280mV produces a stream of ones and zeros that
are high 87.5% of the time. A differential input
of –280mV produces a stream of ones and zeros that
are high 12.5% of the time. The input voltage versus
the output modulator signal is shown in Figure 27.
The system clock of the AMC1203 is 20 MHz by
default, and is generated internally using an RC
circuit. The system clock is divided by two for the
modulator clock; thus, the default clock frequency of
the modulator is 10MHz. This clock is also available
on the output terminal MCLK, whereas the data are
provided at the MDAT output pin. The data are
changing at the falling edge of MCLK, so data can
safely be latched with the rising edge; see the Timing
Characteristics.
FILTER USAGE
The modulator generates a bit stream that is
processed by a digital filter to get a digital word
similar to the conversion result of a conventional
analog-to-digital converter (ADC). A very simple filter,
built with minimal effort and hardware, is a sinc³ filter:
3
H(z) =
1 - z^-OSR
1 - z^-1
(1)
This filter provides the best output performance at the
lowest hardware size (count of digital gates). For an
OSR in the range of 16 to 256, this filter is a good
choice. All the characterizations in this document are
also done with a sinc³ filter with OSR=256 and an
output word width of 16 bits.
In a sinc³ filter response (shown in Figure 25 and
Figure 26), the location of the first notch occurs at the
frequency of output data rate f_DATA = f_CLK/OSR.
The –3dB point is located at half the Nyquist
frequency or f_DATA/4.
SBAS427C – FEBRUARY 2008 – REVISED JUNE 2011
0
-10
-20
-30
-40
-50
-60
-70
-80
0
f_DATA = 10MHz/32 = 312.5kHz
-3dB: 81.9kHz
OSR = 32
200 400 600 800 1000 1200 1400 1600
Frequency (kHz)
Figure 25. Frequency Response of the Sinc³
Filter
30k
f_MOD = 10MHz
OSR = 32
25k _{FSR = 32768}
ENOB = 9.9 Bits
20k Settling Time =
3 ´ 1/f_DATA = 9.6ms
15k
10k
5k
0
0
5 10 15 20 25 30 35 40
Number of Output Clocks
Figure 26. Pole Response of the Sinc³ Filter
Performance can be improved, for example, by using
a cascaded filter structure. The first decimation stage
could be built using a sinc³ filter with a low OSR and
the second stage using a high-order filter.
Modulator Output
+FS (Analog Input)
Analog Input
Figure 27. Analog Input vs Modulator Output
-FS (Analog Input)
Copyright © 2008–2011, Texas Instruments Incorporated
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