AMC1203_15 Datasheet, PDF (14/29 Pages) Texas Instruments – 1-Bit, 10MHz, 2nd-Order, Isolated Delta-Sigma Modulator

AMC1203
SBAS427C – FEBRUARY 2008 – REVISED JUNE 2011
THEORY OF OPERATION
www.ti.com
The differential analog input of the AMC1203 is
implemented with a switched-capacitor circuit. This
switched-capacitor circuit implements a 2nd-order
modulator stage that digitizes the input signal into a
1-bit output stream. The internally-generated clock
signal (sourcing the capacitor circuit and the
modulator) is available as an output signal on the
MCLK pin. The analog input signal is continuously
sampled by the modulator and compared to an
internal voltage reference. A digital stream, accurately
representing the analog input voltage over time,
appears at the output of the converter.
ANALOG INPUT
The input design topology of the AMC1203 is based
on a fully-differential, switched-capacitor architecture
with a dynamic input impedance of 28kΩ at 10MHz,
as Figure 1 shows. This input stage provides the
mechanism to achieve low system noise, high
common-mode rejection (92dB), and excellent
power-supply rejection.
The input impedance becomes a consideration in
designs with high input-signal source impedance.
This high-impedance may cause degradation in gain,
linearity, and THD. The importance of this effect,
however, depends on the desired system
performance.
There are two restrictions on the analog input signals,
V_IN+ and V_IN–. If the input voltage exceeds the range
GND – 0.3V to V_DD + 0.3V, the input current must be
limited to 10mA, because the input protection diodes
on the front end of the converter begin to turn on. In
addition, the linearity and the noise performance of
the device is ensured only when the differential
analog voltage resides within ±280mV.
MODULATOR
The modulator topology of the AMC1203 is
fundamentally a 2nd-order, switched-capacitor,
delta-sigma modulator, such as the one
conceptualized in Figure 24. The analog input voltage
(X_(t)) and the output of the 1-bit digital-to-analog
converter (DAC) are differentiated, providing an
analog voltage (X₂) at the input of the first integrator
or modulator stage. The output of the first integrator
is further differentiated with the DAC output, and the
resulting voltage (X₃) feeds the input of the second
integrator stage. When the value of the integrated
signal (X₄) at the output of the second stage equals
the comparator reference voltage, the output of the
comparator switches from high to low, or vice versa,
depending on its previous state. In this case, the 1-bit
DAC responds on the next clock pulse by changing
its analog output voltage (X₆), causing the integrators
to progress in the opposite direction, while forcing the
value of the integrator output to track the average of
the input.
X_(t)
X₂
Integrator 1
f_S
X₃
X₄
Integrator 2
V_REF
f_CLK
DATA
Comparator
X₆
DAC
Figure 24. Block Diagram of the 2nd-Order Modulator
14
Copyright © 2008–2011, Texas Instruments Incorporated