TMS320C6454 Datasheet, PDF (143/225 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.8.3.3 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 7-26 and described in Table 7-35.
31
16
Reserved
R-0
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Reserved
R-0
1
0
GOSTAT
R-0
Figure 7-26. PLL Controller Status Register (PLLSTAT) [Hex Address: 029C 013C]
Table 7-35. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit Field
31:1 Reserved
0 GOSTAT
Value
0
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation status.
Go operation is not in progress. SYSCLK divide ratios are not being changed.
GO operation is in progress. SYSCLK divide ratios are being changed.
7.8.3.4 PLL Controller Clock Align Control Register
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in
Table 7-26.
31
16
Reserved
R-0
15
Reserved
1
0
ALN1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
R/W-1
Figure 7-27. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029C 0140]
Table 7-36. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit Field
31:1 Reserved
0 ALN1
Value
0
0
1
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLK1 alignment. Do not change the default values of these fields.
Do not align SYSCLK1 during GO operation. If SYS1 in DCHANGE is set to 1, SYSCLK1 switches
to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLK1 when the GOSET bit in PLLCMD is set. The SYSCLK1 ratio is set to the ratio
programmed in the RATIO bit in PLLDIV1.
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C64x+ Peripheral Information and Electrical Specifications 143