TMS664414 Datasheet, PDF (14/56 Pages) Texas Instruments – 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
auto refresh
Before performing an auto refresh, all banks must be deactivated (placed in precharge). To enter a REFR
command, RAS and CAS must be low and W must be high during the rising edge of CLK (see Table 1). The
refresh address is generated internally such that after 4096 REFR commands, all banks of the ’664xx4 are
refreshed. The external address and bank-select A12 – A13 are ignored. The execution of a REFR command
automatically deactivates all banks upon completion of the internal auto-refresh cycle. This allows consecutive
REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR
commands do not necessarily have to be consecutive, but all 4096 must be completed before t_REF expires.
self-refresh mode
To enter self-refresh mode, all banks of the ’664xx4 must be deactivated first and an SLFR command must be
executed (see Table 2). The SLFR command is identical to the REFR command except that CKE is low. For
proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK when RAS and CAS
are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, refreshing
signals are generated internally for all banks with all external signals (except CKE) being ignored. Data can be
retained by the device automatically for an indefinite period when power is maintained (consumption is reduced
to a minimum). To exit self-refresh mode, CKE must be brought high. New commands are issued after t_RC has
expired. If CLK is made inactive during self-refresh, it must be returned to an active and stable condition before
CKE is brought high to exit self-refresh mode (see Figure 19).
Prior to entering and upon exiting self-refresh mode, 4096 REFR commands are recommended before
continuing with normal device operations. This ensures that the SDRAM is fully refreshed.
interrupted bursts
A read or write can be interrupted before the burst sequence is complete with no adverse effects to the operation.
This is accomplished by entering certain superseding commands as listed in Table 7 and Table 8, provided that
all timing requirements are met. The interruption of READ-P and WRT-P operations is not supported.
Table 7. Read-Burst Interruption
INTERRUPTING COMMAND
READ, READ-P
WRT, WRT-P
DEAC, DCAB
EFFECT OR NOTE ON USE DURING READ BURST
Current output cycles continue until the programmed latency from the superseding READ (READ-P)
command is met and new output cycles begin (see Figure 3).
The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention,
DQMx must be high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD–1),
nCCD, and (nCCD+1), assuming there is any output on these cycles (see Figure 4).
The DQ bus is in the high-impedance state when nHZP cycles are satisfied or upon completion of the read
burst, whichever occurs first (see Figure 5 and Figure 22).
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