TMS664414 Datasheet, PDF (1/56 Pages) Texas Instruments – 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
D Organization . . .
1 048 576 x 16 Bits x 4 Banks
2 097 152 x 8 Bits x 4 Banks
4 194 304 x 4 Bits x 4 Banks
D 3.3-V Power Supply (± 10% Tolerance)
D Four Banks for On-Chip Interleaving for
x8/x16 (Gapless Access) Depending on
Organizations
D High Bandwidth – Up to 125-MHz Data
Rates
D Burst Length Programmable to 1, 2, 4, 8
D Programmable Output Sequence – Serial or
Interleave
D Chip-Select and Clock-Enable for
Enhanced-System Interfacing
D Cycle-by-Cycle DQ Bus Mask Capability
D Only x16 SDRAM Configuration Supports
Upper-/Lower-Byte Masking Control
D Programmable CAS Latency From Column
Address
D Performance Ranges:
D Pipeline Architecture (Single-Cycle
Architecture)
D Single Write/Read Burst
D Self-Refresh Capability (Every 16 ms)
D Low-Noise, Low-Voltage
Transistor-Transistor Logic (LVTTL)
Interface
D Power-Down Mode
D Compatible With JEDEC Standards
D 16K RAS-Only Refresh (Total for All Banks)
D 4K Auto Refresh (Total for All Banks)/64 ms
D Automatic Precharge and Controlled
Precharge
D Burst Interruptions Supported:
– Read Interruption
– Write Interruption
– Precharge Interruption
D Support Clock-Suspend Operation (Hold
Command)
D Intel PC100 Compliant (-8 and -8A parts)
’664xx4-8
’664xx4-8A
’664xx4-10
SYNCHRONOUS
CLOCK CYLE
TIME
tCK3
8 ns
tCK2
10 ns
8 ns
15 ns
10 ns
15 ns
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
6 ns
tAC2
6 ns
6 ns
7.5 ns
7.5 ns 7.5 ns
REFRESH
INTERVAL
tREF
64 ms
64 ms
64 ms
description
The TMS664xx4 series are 67 108 864-bit synchronous dynamic random-access memory (SDRAM) devices
which are organized as follow:
D Four banks of 1 048 576 words with 16 bits per word
D Four banks of 2 097152 words with 8 bits per word
D Four banks of 4 194304 words with 4 bits per word
All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed
microprocessors and caches.
The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP)
(DGE suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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