TMS320C28346 Datasheet, PDF (132/153 Pages) Texas Instruments – Delfino Microcontrollers

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516 – MARCH 2009
www.ti.com
Table 6-38. External Interface Read Switching Characteristics (continued)
PARAMETER
MIN
MAX UNIT
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_d(XCOHL-XRDH
t_h(XA)XZCSH
t_h(XA)XRD
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–0.2
–0.4
(1)
(1)
0.57 ns
0.4 ns
0.4 ns
ns
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
(A)(B)
XCLKOUT = XTIMCLK^(D)
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
XWE, XWE1^(E)
Lead
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
Active
t_{d(XCOHL-XRDL)}
Trail
(C)
t_{d(XCOHL-XZCSH)}
t_{d(XCOHL-XRDH)}
t_su(XD)XRD
XR/W
XD[0:31], XD[0:15]
XREADY^(F)
t_a(A)
t_a(XRD)
t_h(XD)XRD
DIN
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-21. Example Read Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
≥2
XRDACTIVE
≥6
XRDTRAIL
≥0
USEREADY
0
X2TIMING
0
XWRLEAD
N/A ⁽¹⁾
XWRACTIVE
N/A ⁽¹⁾
XWRTRAIL
N/A ⁽¹⁾
(1) N/A = Not applicable (or “Don’t care”) for this example
6.15.6 External Interface Write Timing
READYMODE
N/A ⁽¹⁾
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XWEL)}
Table 6-39. External Interface Write Switching Characteristics
PARAMETER
MIN
Delay time, XCLKOUT high to zone chip-select active low
0
Delay time, XCLKOUT high or low to zone chip-select inactive high
–0.2
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 low
–0.5
MAX
2
0.9
0.57
0.5
UNIT
ns
ns
ns
ns
132 Electrical Specifications
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