BQ4010_07 Datasheet, PDF (13/18 Pages) Texas Instruments – 8 k x 8 NONVOLATILE SRAM (5 V, 3.3 V)

bq4010/Y/LY
www.ti.com
SLUS116A – MAY 1999 – REVISED APRIL 2007
Table 4. 5-V POWER-DOWN/POWER-UP (T_A = T_OPR)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾ MAX UNIT
t_PF
V_CC slew, 4.75 to 4.25 V
t_FS
V_CC slew, 4.25 to V_SO
t_PU
V_CC slew, V_SO to V_{PFD (max.)}
300
µs
10
µs
0
µs
t_CER
Chip enable recovery time
Time during which SRAM is write-protected after
V_CC passes V_PFD on power-up.
t_DR
Data-retention time in absence of V_CC T_A = 25°C⁽²⁾
40
80 120 ms
10
years
t_WPT
Write-protect time
Delay after V_CC slews down past V_PFD before SRAM
is writeprotected.
40 100 150 µs
(1) Typical values indicate operation at T_A = 25°C, V_CC = 5V.
(2) Batteries are disconnected from circuit until after V_CC is applied for the first time. t_DR is the accumulated time in absence of power
beginning when power is first applied to the device.
V_CC
CE
t_PF
4.75 V
V_PFD
t_FS
t_WPT
4.25 V
V_SO
V_SO
t_DR
V_PFD
t_PU
t_CER
Figure 10. 5-V Power-Down/Power-Up Timing
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