SMJ320MCM42C Datasheet, PDF (12/16 Pages) Texas Instruments – DUAL SMJ320C40 MULTICHIP MODULE

SMJ320MCM42C, SMJ320MCM42D
DUAL SMJ320C40 MULTICHIP MODULE
SGKS001B – JULY 1997 – REVISED FEBRUARY 2000
capacitance
Capacitance of a ’C40 die is specified by design to be 15 pF maximum for both inputs and outputs. Module
networks add up to 5 pF. Characterization of die or substance capacitance is performed after any design
change. Power measurements taken for a ’C40 die are made with an additional 80-pF load capacitance. Refer
to the SMJ320C40 data sheet (literature number SGUS017) for the test load circuit.
operational timings and module testing
Texas Instruments processing assures that operation is verified to published data sheet specifications on the
’C40 in die form. All voltage, timing, speed, and temperature specifications are met before any die is placed into
a multichip module. For this reason, all ’C40 voltage and timing parameters at the module level need not be
verified.
Characterization of the ’42 substrate shows that the module performs as an equivalent system of discretely
packaged ’C40 devices. This performance is assured through a full-frequency functional checkout of the module
that verifies selected worst-case timings. An additional propagation delay is introduced by the substrate. This
value is assured by design to be less than 1 ns, but it is not tested. See the SMJ320C40 data sheet (literature
number SGUS017) for a complete listing of timing diagrams and limits.
module test capability (future compatibility)
The ’C40 supports the IEEE-1149.1 testability standard, and the test access port (TAP) is brought out to the
module footprint. TDI is connected to ’C40_#1, TDO of ’C40_#1 is connected to TDI of ’C40_#2, and TDO of
’C40_#2 is brought out to the TAP. TCK_COMM, TMS_COMM, and TRST_COMM are routed to both ’C40s in
the module. This configuration allows users to test the module using third-party JTAG testability tools or other
boundary-scan control software. Proper software configuration allows users to debug or launch code on the
module by way of the ’C40 emulator and extended development system (XDS™) pod. Both of these tools are
used as part of outgoing module testing.
The ’42 supports third-party JTAG diagnostic families of products for verification and debug of boundary-scan
circuits, boards, and systems. Further information on JTAG testability tools is available through any TI sales
representative or authorized TI distributor.
XDS is a trademark of Texas Instruments Incorporated.
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