LP38859_15 Datasheet, PDF (11/25 Pages) Texas Instruments – 3A Fast-Response High-Accuracy LDO Linear Regulator With Soft Start

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LP38859
SNVS337F – JUNE 2006 – REVISED SEPTEMBER 2015
Feature Description (continued)
7.3.3 Undervoltage Lockout
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the undervoltage lockout (UVLO) threshold of approximately 2.45 V.
As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the minimum operating rating value of 3 V, the device
is functional, but the operating parameters are not within the specified limits.
7.3.4 Supply Sequencing
There is no requirement for the order that V_IN or V_BIAS are applied or removed.
One practical limitation is that the soft-start circuit starts charging C_SS when V_BIAS rises above the UVLO
threshold. If the application of V_IN is delayed beyond this point the benefits of soft start are compromised.
In any case, the output voltage cannot be specified until both V_IN and V_BIAS are within the range of specified
operating values.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin
must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.
7.3.5 Reverse Voltage
A reverse voltage condition exists when the voltage at the output pin is higher than the voltage at the input pin.
Typically this happens when V_IN is abruptly taken low and C_OUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there is no reverse current flow through the pass element during a reverse voltage event.
The gate of the pass element is not driven when V_BIAS is below the UVLO threshold.
When V_BIAS is above the UVLO threshold, the control circuitry is active and attempts to regulate the output
voltage. Because the input voltage is less than the output voltage the control circuit drives the gate of the pass
element to the full V_BIAS potential when the output voltage begins to fall. In this condition, reverse current flows
from the OUT pin to the IN pin , limited only by the R_DS(ON) of the pass element and the output to input voltage
differential. This condition is outside the specified operating range and must be avoided.
7.3.6 Soft-Start
The LP38859 incorporates a soft-start function that reduces the start-up current surge into the output capacitor
(C_OUT) by allowing V_OUT to rise slowly to the final value. This is accomplished by controlling V_REF at the SS pin.
The soft-start timing capacitor (C_SS) is internally held to ground until V_BIAS rises above the UVLO threshold.
V_REF rises at an RC rate defined by the internal resistance of the SS pin (r_SS), and the external capacitor
connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state
regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is
sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in
current limit.
Soft-Start Time = C_SS × r_SS × 5
(1)
Because the V_OUT rise is exponential, not linear, the in-rush current peaks during the first time constant (τ), and
V_OUT requires four additional time constants (4τ) to reach the final value (5τ) .
After achieving normal operation, if V_BIAS falsl below the ULVO threshold, the device output is disabled, and the
soft-start capacitor (C_SS) discharge circuit becomes active. The C_SS discharge circuit remains active until V_BIAS
falls to 500 mV (typical). When V_BIAS falls below 500 mV (typical), the C_SS discharge circuit ceases to function
due to a lack of sufficient biasing to the control circuitry.
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