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BQ24257 Datasheet, PDF (11/45 Pages) Texas Instruments – 2A Single Input I2C, Standalone Switch-Mode Li-Ion Battery Charger with Integrated Current Sense Resistor
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PIN NAME
IN
bq24257
YFF
A5,B5,C5
bq24257
RGE
19
bq24258
YFF
A5,B5,C5
bq24258
RGE
19
PMID
D5
20
D5
20
SW
BOOT
A4,B4,C4
E5
17-18
21
A4,B4,C4
E5
17-18
21
PGND
CSIN
A3,B3,C3,
F3
A2,B2,C2
15-16
13-14
A3,B3,C3,
D3,F3
A2,B2,C2
15-16
13-14
BAT
A1,B1,C1 11-12 A1,B1,C1 11-12
TS
F1
9
F1
9
VDPM
E4
23
E4
23
ISET
D1
10
D1
10
ILIM
F5
22
F5
22
CE
D4
1
D4
1
EN1
--
--
F2
5
EN2
--
--
E2
6
EN3
--
--
D2
3
PG
E1
8
E1
8
STAT
E3
7
E3
7
NC
--
--
--
2
SCL
E2
6
--
--
SDA
F2
5
D+
D3
2
--
--
D-
D2
3
--
--
LDO
F4
24
F4
24
AGND
--
4
--
4
PIN FUNCTIONS
I/O
DESCRIPTION
bq24257
bq24258
SLUSBG0B – FEBRUARY 2013 – REVISED JULY 2013
I
Input power supply. IN is connected to the external DC supply (AC adapter or
USB port). Bypass IN to PGND with >2 μF ceramic capacitor
I
Connection between blocking FET and high-side FET. Connect a 1 μF capacitor
from PMID to PGND as close to the PMID and PGND pins as possible
O
Inductor Connection. Connect to the switching side of the external inductor.
I
High Side MOSFET Gate Driver Supply. Connect a 0.033 μF ceramic capacitor
(voltage rating > 15 V) from BOOT to SW to supply the gate drive for the high
side MOSFETs.
Power Ground terminal. Connect to the ground plane of the circuit. For QFN
only, connect to the thermal pad of the IC.
I
System Voltage Sense and SMPS output filter connection. Connect CSIN to the
system output at the output bulk capacitors. Bypass CSIN locally with at least 1
μF.
I/O
Battery Connection. Connect to the positive terminal of the battery. Additionally,
bypass BAT with at least 20 μF capacitor to GND.
I
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider
from LDO to GND. The NTC is connected from TS to GND. The TS function
provides 4 thresholds for JEITA or PSE compatibility. See the NTC Monitor
section for more details on operation and selecting the resistor values.
I
Input DPM Programming Input. Connect a resistor divider between IN and GND
with VDPM connected to the center tap to program the Input Voltage based
Dynamic Power Management threshold (VIN_DPM). The input current is
reduced to maintain the supply voltage at VIN_DPM. The reference for the
regulator is 1.2 V. Short pin to GND if external resistors are not desired—this
sets a default of 4.36 V for the input DPM threshold.
I
Charge Current Programming Input. Connect a resistor from ISET to GND to
program the fast charge current.
I
Input Current Limit Programming Input. Connect a resistor from ILIM to GND to
program the input current limit for IN. The current limit is programmable from
0.5A to 2A. ILIM has no effect on the USB input. If an external resistor is not
desired, short to GND for a 2 A default setting.
I
Charge Enable Active-Low Input. Connect CE to a high logic level to place the
battery charger in standby mode.
I
Input Current Limit Configuration Inputs. Use EN1, EN2, and EN3 to control the
I
maximum input current and enable USB compliance. See Table 1 for
programming details.
I
O
Power Good Open Drain Output. /PG is pulled low when a valid supply is
connected to IN. A valid supply is between VBAT+VSLP and VOVP. If no supply
is connected or the supply is out of this range, /PG is high impedance.
O
Status Output. STAT is an open-drain output that signals charging status and
fault interrupts. STAT pulls low during charging. STAT is high impedance when
charging is complete or the charger is disabled. When a fault occurs, a 256 μs
pulse is sent out as an interrupt for the host. STAT is enabled/disabled using the
EN_STAT bit in the control register. STAT will indicate recharge cycles. Connect
STAT to a logic rail using an LED for visual indication or through a 10 kΩ
resistor to communicate with the host processor.
Not connected
I
I2C Interface Clock. Connect SCL to the logic rail through a 10 kΩ resistor.
I/O
I2C Interface Data. Connect SDA to the logic rail through a 10 kΩ resistor.
I
BC1.2 compatible D+/D- Based Adapter Detection. Detects DCP, SDP, and
I
CDP. Also complies with the unconnected dead battery provision clause. D+
and D- are connected to the D+ and D- outputs of the USB port at power up.
Also includes the detection of Apple™ and TomTom™ adapters where a 500mA
input current limit is enabled.
O
LDO output. LDO is regulated to 4.9 V and drives up to 50 mA. Bypass LDO
with a 1μF ceramic Capacitor. LDO is enabled when VUVLO < VIN < 19 V.
Analog Ground for QFN only. Connect to the thermal pad and the ground plane
of the circuit.
Copyright © 2013, Texas Instruments Incorporated
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