NTE4052BT Datasheet, PDF (10/28 Pages) Texas Instruments – Data sheet acquired from Harris Semiconductor

CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms (Continued)
V_DD
V_DD
V_DD
1
16
2
15
I_DD
3
14
4
13
5
12
6
11
7
10
8
9
CD4051
1
16
2
15
I_DD
3
14
4
13
5
12
6
11
7
10
8
9
CD4052
1
16
2
15
I_DD
3
14
4
13
5
12
6
11
7
10
8
9
CD4053
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
V_DD
V_EE
V_SS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CD4051
V_DD
OUTPUT _OUTPUT
R_L
C_{L CL}
R_L
V_EE
V_DD
V_DD
V_{SS CLOCK}
IN
V_{EE VEE}
V_SS
V_SS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CD4052
V_DD
V_DD
V_EE
V_SS
CLOCK
IN
V_SS
V_SS
V_DD
1
16
OUTPUT
2
15
3
14
R_L
C_L
4
13
5
12 _VDD
V_EE
6
11
7
10 ^{VSS CLOCK}
8
9
IN
CD4053 ^VSS
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
OUTPUT
V_DD
1
16
R_L
50pF 2
15
3
14
V_EE 4
13
V_DD
V_DD
V_{SS CLOCK VEE}
5
6
7
12
11
10
IN _VSS
8
9
t_PHL AND t_PLH ^VSS
CD4051
OUTPUT
V_DD
1
16
R_L
50pF 2
15
3
14
V_{EE 4}
13
V_DD
V_DD
5
12
6
11
V_SS
CLOCK
IN
V_EE
V_SS
7
8
10
9
t_PHL AND t_PLH^VSS
CD4052
OUTPUT
1
R_L
50pF
2
3
V_DD
V_EE
4
V_DD ⁵
6
V_{SS CLOCK} V_EE 7
IN V_SS 8
16
V_DD
15
14
13
12
11
10
9
t_PHL AND t_PLH^VSS
CD4053
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
V_DD
µA
V_IH
1K
1K
V_IH
V_IL
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4051B
V_IL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
V_DD
1 16
2 15
1K
µA
3 14
V_IH
4 13
5 12 1K
6 11
V_IL
7 10
89
V_IH
CD4052B
V_IL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
V_DD
1K
V_IH
V_IL
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CD4053B
µA
1K
V_IH
V_IL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
10