BQ3060 Datasheet, PDF (10/17 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE and PROTECTION with CEDV

bq3060
SLUS928A – MARCH 2009 – REVISED NOVEMBER 2009
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SMBus
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
f_SMB
f_MAS
t_BUF
t_HD:STA
t_SU:STA
t_SU:STO
t_HD:DAT
SMBus operating frequency
SMBus master clock frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup time
Stop setup time
Data hold time
Slave mode, SMBC 50% duty cycle
Master mode, no clock low slave extend
Receive mode
Transmit mode
10
51.2
4.7
4.0
4.7
4.0
0
300
100 kHz
kHz
μs
μs
μs
μs
ns
t_SU:DAT
t_TIMEOUT
t_LOW
t_HIGH
t_LOW:SEXT
t_LOW:MEXT
t_F
t_R
Data setup time
Error signal/detect
Clock low period
Clock high period
Cumulative clock low slave extend time
Cumulative clock low master extend
time
Clock/data fall time
Clock/data rise time
See ⁽¹⁾
See ⁽²⁾
See ⁽³⁾
See ⁽⁴⁾
See ⁽⁵⁾
See ⁽⁶⁾
250
ns
25
35 ms
4.7
μs
4.0
50 μs
25 ms
10 ms
300 ns
1000 ns
(1) The bq3060 times out when any clock low exceeds t_TIMEOUT
(2) t_HIGH, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 μs causes reset of any transaction involving bq3060 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). If NC_SMB is set then
the timeout is disabled.
(3) t_LOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t_LOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time t_R = V_ILMAX – 0.15) to (V_IHMIN + 0.15)
(6) Fall time t_F = 0.9V_DD to (V_ILMAX – 0.15)
Timing Measurement Intervals
SCLK
t _LOW
tR
tF
t HD:STA
SDATA
P
t HD:STA
t HD:DAT
t HIGH
t SU:STA
t SU:DAT
t SU:STO
t _BUF
S
S
P
SCLK
Start
t _{TIMEOUT Measurement Intervals}
t _LOW:MEXT
t _LOW:SEXT
SCLK
1
ACK
t _LOW:MEXT
Stop
SCLK
1
ACK
t _LOW:MEXT
SDATA
(1) SCLK_ACK is the acknowledge-related clock pulse generated by the master.
10
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