SN74ALVCH16831 Datasheet, PDF (1/9 Pages) Texas Instruments – 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS

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FEATURES
• Member of the Texas Instruments Widebus™
Family
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 1-bit to 4-bit address register/driver is designed
for 1.65-V to 3.6-V V_CC operation. The device is ideal
for use in applications in which a single address bus
is driving four separate memory locations. The
SN74ALVCH16831 can be used as a buffer or a
register, depending on the logic level of the select
(SEL) input.
When SEL is logic high, the device is in the buffer
mode. The outputs follow the inputs and are
controlled by the two output-enable (OE) controls.
Each OE controls two groups of nine outputs.
When SEL is logic low, the device is in the register
mode. The register is an edge-triggered D-type
flip-flop. On the positive transition of the clock (CLK)
input, data set up at the A inputs is stored in the
internal registers. OE controls operate the same as in
buffer mode.
When OE is logic low, the outputs are in a normal
logic state (high or low logic level). When OE is logic
high, the outputs are in the high-impedance state.
SEL and OE do not affect the internal operation of
the flip-flops. Old data can be retained or new data
can be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to V_CC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not
recommended.
SN74ALVCH16831
1-TO-4 ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES083F – AUGUST 1996 – REVISED SEPTEMBER 2004
DBB PACKAGE
(TOP VIEW)
4Y1 ₁
3Y1 2
GND 3
2Y1 4
1Y1 5
V_CC 6
NC 7
A1 8
GND 9
NC 10
A2 11
GND 12
NC 13
A3 14
V_CC 15
NC 16
A4 17
GND 18
CLK 19
OE1 20
OE2 21
SEL 22
GND 23
A5 24
A6 25
V_CC 26
A7 27
NC 28
GND 29
A8 ³⁰
NC ³¹
GND ³²
A9 ³³
NC ³⁴
V_CC ³⁵
4Y9 ³⁶
3Y9 ³⁷
GND ³⁸
2Y9 ³⁹
1Y9 ⁴⁰
80 1Y2
79 2Y2
78 GND
77 3Y2
76 4Y2
75 V_CC
74 1Y3
73 2Y3
72 GND
71 3Y3
70 4Y3
69 GND
68 1Y4
67 2Y4
66 V_CC
65 3Y4
64 4Y4
63 GND
62 1Y5
61 2Y5
60 3Y5
59 4Y5
58 GND
57 1Y6
56 2Y6
55 VCC
54 3Y6
53 4Y6
52 ^GND
51 1Y7
50 2Y7
49 ^GND
48 ^3Y7
47 ^4Y7
46 ^VCC
45 ^1Y8
44 ^2Y8
43 ^GND
42 ^3Y8
41 ^4Y8
NC − No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2004, Texas Instruments Incorporated