ADS62P15_09 Datasheet, PDF (1/64 Pages) Texas Instruments – Dual Channel 11-Bits,125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

ADS62P15
www.ti.com .................................................................................................................................................... SLAS572B – OCTOBER 2007 – REVISED APRIL 2009
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
FEATURES
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• Maximum Sample Rate: 125 MSPS
• 11-Bit Resolution With No Missing Codes
• 84 dBc SFDR at Fin = 50 MHz
• 67.1 dBFS SNR at Fin = 50 MHz
• 92 dB Crosstalk
• Parallel CMOS and DDR LVDS Output Options
• 3.5 dB Coarse Gain and Programmable Fine
Gain up to 6 dB for SNR/SFDR Trade-Off
• Digital Processing Block With:
– Offset Correction
– Fine Gain Correction, in Steps of 0.05 dB
– Decimation by 2/4/8
– Built-in and Custom Programmable 24-Tap
Low/High /Band Pass Filters
• Supports Sine, LVPECL, LVDS & LVCMOS
Clocks & Amplitude Down to 400 mV_PP
• Clock Duty Cycle Stabilizer
• Internal Reference; Supports External
Reference also
• 64-QFN Package (9mm × 9mm)
• Pin Compatible 14-bit and 12-bit Family
(ADS62P4X/ADS62P2X)
APPLICATIONS
• Wireless Communications Infrastructure
• Software Defined Radio
• Power Amplifier Linearization
• 802.16d/e
• Medical Imaging
• Radar Systems
• Test and Measurement Instrumentation
Table 1. ADS62PXX Dual Channel Family
ADS62P4X
(14 bit)
ADS62P2X
(12 bit)
(11 bit)
125 MSPS
ADS62P45
ADS62P25
ADS62P15
105 MSPS
ADS62P44
ADS62P24
-
80 MSPS
ADS62P43
ADS62P23
-
65 MSPS
ADS62P42
ADS62P22
-
DESCRIPTION
ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high
performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and
low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and
fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62P15 includes a digital processing block that consists of several useful and commonly used digital
functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and
in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions
are disabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes
internal references while traditional reference pins and associated decoupling capacitors have been eliminated.
Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial
temperature range (–40°C to 85°C).
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated