THC7984_15 Datasheet, PDF (40/46 Pages) THine Electronics, Inc. – 10-bit 3-channel Video Signal Digitizer

THC7984_Rev.2.0_E
R31[0] HSYNC Period Measurement Run
0: Stop the Measurement of HSYNC Period.
1: Start Measurement of HSYNC Period. (A result of measurement is renewed every 100 lines.) .
*When reading the result of measurement (R32[3:0] / R33[7:0] / R34[7:0]) , please suspend measurement.
R32[3:0]/R33[7:0]/R34[7:0] HSYNC Period Measurement Result
The period of 100 lines of horizontal period is counted by External REFCLK and the result can be read.
The horizontal period and frequency are calculated by the following formula.
Horizontal period [us] = Measurement result / (100 * fREFCLK)
Horizontal Frequency [kHz] = fREFCLK * 10⁵ / Measurement result
* fREFCLK is REFCLK frequency (unit :MHz)
*Input a reference clock (7-40MHz) to CLAMP-pin to measure period of Horizontal, and the setting of External REF-
CLK input should be enabled(R31[1]=1) .
*Stop the measurement after more than 20ms(or more than 300 lines) from the start of measurement of horizontal period
(R31[0]=1), and read the result(R32[3:0] / R33[7:0] / R34[7:0]) .
R35[7] Sync Signal Valid Flag (Event Recorder)
1 is set when HSYNC and VSYNC are detected in input sync. At this point, all the measurement and detection are
completed.
R35[4] Port-1 Input Sync Type Change Detection (Event Recorder)
R35[3] Port-0 Input Sync Type Change Detection (Event Recorder)
1 is set when Port-1 Input Sync Type Detection (R2C[6:5]) , Port-0 Input Sync Type Detection (R2C[4:3]) changes.
R35[2] Input Signal Format Change Detection
When following even one detection and result of measurement changed, 1 is set
HSYNC Input polarity Detection
VSYNC Input polarity Detection
Vertical Total Line Measurement (Change detection threshod(R37[7:5]) default setting is +/-1 line)
VSYNC Input Pulse Width Measurement (Change detection threshold (R37 [4:3]) default setting:+/- 1 line.)
HSYNC Period Measurement (Change detection threshold (R37 [2:0]) default setting:+/- 64)
*It's possible to detect the switching of seamless input format change of which the input SYNC type doesn't change.
R35[1] Input HSYNC Missing Edge Detection (Event Recorder)
1 is set when HSYNC edges are not detected inside the prospective period. The PLL COAST period (R22[6:0]/R23[6:0])
is not the subject of detection.
* In case input sync signal includes no pulses during the vertical sync time such as OR-type CSYNC, these missing
pulses should be covered by PLL COAST signal.
R35[0] Input HSYNC Extraneous Edge Detection (Event Recorder)
‘1’ is read when HSYNC edges are detected outside the prospective period. The PLL COAST period (R22[6:0]/
R23[6:0]) is not the subject of detection.
* In case input sync signal includes extraneous pulses such as equalization pulses and copy protection signal during the
vertical blank time, these pulses should be covered by PLL COAST signal or eliminated by HSYNC Filter (R1F[4]) .
* Event recorders must be cleared by writing 1 to them to start the measurement and detection by them.
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