THC7984_15 Datasheet, PDF (35/46 Pages) THine Electronics, Inc. – 10-bit 3-channel Video Signal Digitizer

THC7984_Rev.2.0_E
R1F[6:5] Reserved *Must be set to 00b for proper operation (Default value: 00b)
R1F[4] PLL HSYNC Filter Enable
By using Filtered HSYNC generated by HSYNC Filter that eliminates the extraneous pulses such as equalization pulses
and copy protection signal from the HSYNC input (Raw HSYNC) , the PLL COAST period (PLL free-run period) can
be set shorter. However, the HSYNC input with high jitter makes HSYNC Filter Window unstable and possibly causes
PLL unlock.
0: Raw HSYNC is used as the reference signal of PLL.
1: Filtered HSYNC is used as the reference signal of PLL.
R1F[3:0] HSYNC Filter Window Width
Set HSYNC Filter Window Width of HSYNC Filter. The setting range is from about +/-100ns (internal oscillator clock
+/-4 cycles) to about +/-1600ns (internal oscillator clock +/-64 cycles) around the leading edge of the HSYNC input
(the leading edge of the positive pulse for 3-level sync) . The setting step is +/-100ns (internal oscillator clock +/-4
cycles) and bigger value results in wider width.
Input HSYNC
with extraneous pulses
Filter Window
< HSYNC Filter >
Input HSYNC Leading Edge
Filter Window Width
Excessive Edge
Filtered HSYNC
Suppressed
Filter Window = High: Not suppressed
Filter Window = Low: Falling Edges are suppressed
*Input HSYNC into HSYNC Filter is always Active-Low
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