U4090B Datasheet, PDF (8/34 Pages) TEMIC Semiconductors – Monolithic Integrated Feature Phone Circuit

U4090B
DC line interface and supply voltage generation
The DC line interface consists of an electronic inductance
and a dual port output stage, which charges the capacitors
at V_MPS and V_B. The value of the equivalent inductance
is given by
L = R_SENSE @ C_IND @ (R_DC @ R₃₀) / (R_DC + R₃₀)In
order to improve the supply during worst case operating
conditions two PNP current sources - I_BOPT and
I_MPSOPT - hand an extra amount of current to the supply
voltages, when the NPNs in parallel are unable to conduct
current.
A flowchart for the control of the current sources
(figure 5) shows, how a priority for supply V_MPS is
achieved.
W ^VL 10 _SENSE
R_SENSE
C_IND
10 mF
I_BOPT
< 5 mA
IND
R_DC
+
–
30 kW
R₃₀
= ^VOFFS
I_MPSOPT
< 5 mA
–
=
+
3.3 V
+
–
6.3 V V_MPS
V_MP
3.3 V/
2 mA
470m F
47 mF
7.0 V
V_B
220m F
94 8047
Figure 4. DC line interface with electronic inductance and generation of a regulated and an unregulated supply
VMPS < 6.3 V
Y _{VSENSE–VMPS>200 mV}
N
N
Y
N IMPSOPT = 0
VSENSE–VB>200 mV
IBOPT = 0
Y
VB < 6.3 V
N
Y
Charge CMPS
(IMPSOPT)
Charge CB
(IBOPT)
Reduce IBOPT
(IMPSOPT = 0)
94 8058
Figure 5. Supply capacitors CMPS and CB are charged with priority on CMPS
8 (34)
TELEFUNKEN Semiconductors
Preliminary Information
Rev. C1, 28-Oct-96