U6239B Datasheet, PDF (7/15 Pages) TEMIC Semiconductors – 2.9 GHz PLL for SAT TV Tuner with UNi-Bus

I²C Bus Description (continued)
Reference divider selection RD1, RD2, RD3:
RD3
RD2
RD1
Reference
Divider Ratio
1
0
0
1
0
1
1
1
0
1
1
1
1024
off
256
512
0
0
0
140
0
0
1
25
0
1
0
250
0
1
1
50
* when a 4MHz crystal is used
Address selection AS1, AS2, AMS:
AMS
AS1
Voltage at Pin 3
< 0.8 V or open
0
< 0.8 V or open
0
< 0.8 V or open
1
< 0.8 V or open
1
> 2.4
0
> 2.4
0
> 2.4
1
> 2.4
1
AS2
Address
0
C0
1
C2
0
C4
1
C6
0
C0
1
C2
0
C4
1
C6
Frequency
Step Size*
62.5 kHz
–
250 kHz
125 kHz
457.14 kHz
2560 kHz
256 kHz
1280 kHz
Dec. Value
192
194
196
198
192
194
196
198
U6239B
Max. Operating
Frequency*
2.047 GHz
–
2.9 GHz
2.9 GHz
2.9 GHz
2.9 GHz
2.9 GHz
2.9 GHz
Voltage at Pin 10
0 to 10% V_S
always valid
40 to 60% V_S
90% V_S to 13.2 V
0 to 10% V_S
open
40 to 60% V_S
90% V_S to V_S
Read Mode (Address byte LSB = 1)
After the address transmission (first byte), the status byte
can be read from the device on the SDA line (MSB first).
Data is valid on the SDA line during logic high of the SCL
signal. The controller accepting the data has to pull the
SDA line to low-level during all status-byte acknowledge
periods to read another status byte. If the controller fails
to pull the SDA line to low-level during this period, the
device will then release the SDA line to allow the
controller to generate a STOP condition.
The POR bit (power-on-reset) is set to a logic 1 when the
supply voltage V_S of the device has dropped below 3 V
(at 25°C) and also when the device is initially turned on.
The POR bit is reset to a logic 0 when the read sequence
is terminated by a STOP condition. When the POR bit is
set high (at low V_S), this indicates that all the
programmed information is lost and the port outputs are
all set to high impedance state.
The FL bit indicates whether the loop is in phase lock
condition (logic 1) or not (logic 0).
If the ADC or the ports are to be used as inputs, the
corresponding outputs must be programmed to a high
impedance state (logic 1).
The bits I2, I1 and I0 show the status of the I/O ports P7,
P5 and P4 respectively. A logic 0 indicates a LOW level
and a logic 1 a HIGH level (TTL levels).
The bits A2, A1 and A0 represent the digital information
of the 5-level ADC. This converter can be used to feed
AFC information to the controller from the IF section of
the receiver, as shown in the typical application circuit on
page 14.
TELEFUNKEN Semiconductors
Rev. A3, 28-May-97
7 (15)