U6239B Datasheet, PDF (3/15 Pages) TEMIC Semiconductors – 2.9 GHz PLL for SAT TV Tuner with UNi-Bus

U6239B
Functional Description
The U6239B is programmed via a 2-wire I²C bus or
3-wire bus depending on the received data format. In
I²C bus mode the three bus input pins 4, 5, 10 are used as
SDA, SCL and address select inputs or in 3-wire bus
mode as date, clock and enable inputs, respectively. The
data include the scaling factor SF and port output
information. In I²C bus mode there are some additional
functions available (ADC, bidirectional ports, etc.)
Oscillator frequency calculation :
f_VCO = 16 SPF f_refosc/SRF
f_vco: Locked frequency of voltage controlled oscillator
SPF : Scaling factor of programmable divider (15 bit in
I²C bus mode, 14 bit in 3-wire bus mode)
SRF : Scaling factor of reference divider
B B B B B B B ( 25/ 50/ 140/ 250/ 256/ 512/ 1024
B B B B B in I²C bus mode, 25/ 50/ 100/ 140/ 250
B B 280/ 500 in 3-wire bus mode)
f_refosc: Reference oscillator frequency:
3.2/ 4 MHz crystal or external reference
frequency (max. 8 MHz)
The input amplifier together with a divide-by-16
prescaler provides excellent sensitivity (see “Typical
prescaler input sensitivity”). The input impedance is
shown in the diagram “Typical input impedance”. When
a new divider ratio is entered according to the requested
f_VCO, the phase detector and charge pump adjusts the
control voltage of the VCO together with the tuning
amplifier until the output signals of the programmable
divider and the reference divider are in frequency locked
and phase locked. The reference frequency may be pro-
vided by an external source, capacitively coupled into
Pin 2, or by using an on-board crystal with an 18 pF ca-
pacitor in series. The crystal operates in the series
resonance mode. The reference divider division ratio
B B B B B B is selectable to 25/ 50/ 140/ 250/ 256/ 512/
B B B B 1024 in the I²C bus mode and 25/ 50/ 100/
B B B B 140/ 250/ 280/ 500 in the 3-wire bus mode.
In I²C bus mode, the division ratio may be set via three
bits, in 3-wire bus mode via two bits and a voltage at the
reference divider select input Pin 3. In addition, there are
port outputs available for band switching and other
purposes.
Application
A typical application is shown on page 14. All input/
output interface circuits are shown on the pages 12 and
13. Some special features which are related to test- and
alignment procedures for tuner production are explained
together with the bus mode descriptions.
Absolute Maximum Ratings
All voltages are referred to GND (Pin 15)
Parameters
Symbol Conditions
Min.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Supply voltage}
Pin 12
Vs
–0.3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{RF input voltage}
Pins 13, 14
RFi
–0.3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Port output current}
Pins 6-11
P0, P3-7 Open collector
–1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Total port output current
Pins 6-11
P0, P3-7 Open collector
–1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{Port input/ output voltage}
Pins 6-10
P3-7
In off state
–0.3
Port output voltage
Pins 6-11
P0, P3-7 In on state
–0.3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Bus input/ output voltage}
Pins 4 and 5 VSDA,
–0.3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _VSCL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{SDA output current}
Pin 4
ISDA Open collector
–1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Address select/ Enable input Pin 10}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{Port output voltage}
AS/
Port in off
–0.3
ENABLE/
state
P3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Charge pump output voltage Pin 1}
PD
–0.3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Active filter output voltage}
Pin 16
VD
–0.3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Crystal oscillator voltage}
Pin 2
Q1
–0.3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Reference divider select input/ Pin 3}
RDS/
–0.3
Max.
Unit
6
V
Vs + 0.3
V
15
mA
50
mA
14
V
6
V
6
V
5
mA
14
V
Vs + 0.3
V
Vs + 0.3
V
Vs + 0.3
V
V_S + 0.3
V
Address mode select input
AMS
Junction temperature
T_j
–40
125
°C
Storage temperature
T_stg
–40
125
°C
TELEFUNKEN Semiconductors
Rev. A3, 28-May-97
3 (15)