U6239B Datasheet, PDF (6/15 Pages) TEMIC Semiconductors – 2.9 GHz PLL for SAT TV Tuner with UNi-Bus

U6239B
I²C Bus Description
Functional Description
When the U6239B is controlled via a 2-wire I²C bus
format, then data and clock signals are fed into the SDA
and SCL lines respectively. Depending on the LSB of the
address byte, the device can either accept new data (write
mode: LSB = 0) or send data (read mode: LSB = 1).
Depending on the voltage at the address mode select
input, the device has one fixed and three programmable
or four programmable I²C bus addresses. The tables
“I²C bus write data format” and “I²C bus read data
format” describe the format of the data and show how to
select the device addresses by applying the appropriate
voltages at address select Pin 10 and the address mode
select Pin 3.
Write Mode (Address byte LSB = 0)
When write mode is activated and the correct address byte
is received, the SDA line is pulled low by the device
during the acknowledge period. The SDA line is also
pulled low during the acknowledge periods, when addi-
tional data bytes are programmed. After the address
transmission (first byte), data bytes can be sent to the de-
vice. There are four data bytes requested to fully program
the device. Once the correct address is received and ac-
knowledged, the first bit of the following byte determines
whether that byte is interpreted as byte 2 or 4; a logic 0 for
divider information and a logic 1 for control and port out-
put information. If byte 2 has been received, the device
always expects byte 3 next. Likewise if byte 4 has been
received, byte 5 is expected. Additional data bytes can be
entered without the need to re-address the device until an
I²C bus stop condition is recognized. This allows a
smooth frequency sweep for fine tuning AFC purposes.
The table “I²C bus pulse diagram” provides some pos-
sible data transfer examples. In addition, the stop
condition is not a must, the device may be programmed
by using the start condition only.
The programmable divider bytes PDB1 and PDB2 are
stored in a 15-bit latch and control the division ratio of the
15-bit programmable divider. The control byte CB1 en-
ables the controlling of the following special functions:
D 5I bit switches between low and high charge pump
current
D T1 bit enables divider test mode when it is set to
logic 1
D T0 bit enables the charge pump to be disabled when
it is set to logic 1
D RD3, 2 and 1 - bits enable selection of the reference
divider ratio
D OS-bit disables the charge pump drive amplifier out-
put when it is set to logic 1.
The charge pump current can only be controlled in I²C
bus mode. In 3-wire bus mode, the high charge pump cur-
rent is always active.
The OS-bit function disables the complete PLL function.
This enables the tuner alignment by supplying the tuning
voltage directly through the 30 V supply voltage of the
tuner. The control byte CB2 programs the port outputs P0
and P3 - 7.
Description
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Address byte}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Programmable divider, byte 1}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Programmable divider, byte 2}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Control byte 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{Control byte 2}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ A = Acknowledge; X = not used
I²C Bus Data Format
MSB
LSB
1
1
0
0
0 AS1 AS2 0
A
0 n14 n13 n12 n11 n10 n9 n8 A
n7 n6 n5 n4 n3 n2 n1 n0 A
1
5I T1 T0 RD3 RD2 RD1 OS A
P7 P6 P5 P4 P3
X
X
P0
A
n0 to n14 : Scaling factor (SF)
T0, T1 : Test mode selection
P0, 3 to 7: Port outputs
5I :
Charge pump current switch
OS :
Output switch
SF = 16384 n14 + 8192 n13 + ... + 2 n1 + n0
SF - range: 256 to 32767
T1 = 1: divider test mode on, T1 = 0: divider test mode off
FP at Pin 6, FR at Pin 7
T0 = 1: charge pump disable
T0 = 0: charge pump enable
P0, 3, 4, 5, 6, 7 = 1: port active
5I = 1: high current
5I = 0: low current
OS = 1: varicap drive disable OS = 0: varicap drive enable
6 (15)
TELEFUNKEN Semiconductors
Rev. A3, 28-May-97