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TSC80251A1 Datasheet, PDF (66/166 Pages) TEMIC Semiconductors – Extended 8-bit Microcontroller with Analog Interfaces
TSC 80251A1
SCON (098h)
Serial Control register
FE/SM0 OVR/SM1
SM2
REN
TB8
RB8
TI
RI
7
6
5
4
3
2
1
0
Bit
Bit
Number Mnemonic
Description
7
FE
Framing Error bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
SM0 Serial Port Mode bit 0
To select this function, clear SMOD0 bit in PCON register.
Software writes to bits SM0 and SM1 to select the Serial Port operating mode.
Refer to SM1 bit for the mode selections.
6
OVR Overrun error bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an overwrite of the receive buffer.
Must be cleared by software
SM1 Serial Port Mode bit 1
To select this function, clear SMOD0 bit in PCON register.
Software writes to bits SM1 and SMO to select the Serial Port operating mode.
SMO SM1 Mode Description Baud Rate
00
0
Shift register FOSC/12 or variable if SRC bit
BDRCON register is set
01
1
8–bit UART Variable
10
2
11
3
9–bit UART FOSC/32 or FOSC/64
9–bit UART Variable
5
SM2 Serial Port Mode bit 2
Software writes to bit SM2 to enable and disable the multiprocessor
communication and automatic address recognition features.
This allows the Serial Port to differentiate between data and command frames
and to recognize slave and broadcast addresses.
4
REN Receiver Enable bit
Clear to enable transmission. Set to enable reception.
3
TB8 Transmit bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
2
RB8 Receiver bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit
received.
1
TI
Transmit Interrupt flag
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
0
RI
Receive Interrupt flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.
Reset value = 0000 0000B
Figure 4.15. SCON register
II. 4.14
Rev.B (20/09/96)