TSC80251A1 Datasheet, PDF (104/166 Pages) TEMIC Semiconductors – Extended 8-bit Microcontroller with Analog Interfaces

TSC 80251A1
than 6 system clock periods. The B signal is not considered as a glitch and asserts the Power–Fail
interrupt request.
VDD
V_FAIL+
V_FAIL–
A
B
Power–Fail
Window
Power–Fail
Interrupt request
B
A
width < t_FILT (= 6 x 2T_OSC)
width > t_FILT (= 6 x 2T_OSC)
t_FILT = 6 x 2 T_OSC
B
A
Figure 8.5. Waveforms of the VDD filtering
8.4. Power–Off Flag
The POF bit in PCON register is set to 1 when a hardware reset has been applied during the power
is up. This reset is called ”Cold reset”. If a hardware reset is applied during the microcontroller is
running, POF bit is not set. This reset is called ”Warm reset”. This flag allows to distinguish a cold
from a warm reset and initialization. POF bit is useful in Power–Down mode when it is completed
by a hardware reset. When used, this bit must be cleared by software after “Cold reset”.
8.5. Clock Prescaler
In order to optimize the consumption and the execution time needed for a specific task , an internal
clock prescaler feature has been implemented to program the system clock frequency. It is possible
to work at full speed for all tasks requiring quick response time at low frequency for background tasks
which do not need CPU power but consumption optimizing. Figure 8.6. shows the diagram of the
on–chip oscillator where the clock programming block clearly appears. The CPU clock can be
programmed via 8–bit CKRL register and by setting to one CKSRC bit in POWM register:
F_OSC
+
F_XTAL
2(CXRL )
1)
II. 8.4
Rev. B (20/09/96)